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    FinFET spacer without substrate gouging or spacer foot
    1.
    发明授权
    FinFET spacer without substrate gouging or spacer foot 有权

    公开(公告)号：US09793379B2

    公开(公告)日：2017-10-17

    申请号：US14568287

    申请日：2014-12-12

    Applicant: International Business Machines Corporation

    Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Ali Khakifirooz ,  Raghavasimhan Sreenivasan

    IPC: H01L29/66 ,  H01L21/8234

    CPC classification number: H01L29/66795 ,  H01L21/823431

    Abstract: The present invention relates generally to semiconductor devices, and more particularly, to a structure and method of forming a spacer adjacent to a gate in a fin field effect transistor (FinFET) device without resulting in substrate gouging or a spacer foot. A conformal spacer layer may be formed around a plurality of fins and a gate, wherein the conformal spacer layer may have a thickness above the plurality of fins that is at least one-half the distance between the individual fins. An isotropic etch may be used to remove excess spacer material around the plurality of fins (but not between the fins) and around the gate. An anisotropic etch may be used to remove the remaining spacer material from between the fins and around the gate, leaving a spacer adjacent to the gate without gouging the substrate surface between the fins.

    Method and structure for robust finFET replacement metal gate integration
    4.
    发明授权
    Method and structure for robust finFET replacement metal gate integration 有权
    坚固的finFET替代金属栅极集成的方法和结构

    公开(公告)号：US09269792B2

    公开(公告)日：2016-02-23

    申请号：US14299300

    申请日：2014-06-09

    Applicant: International Business Machines Corporation

    Inventor： Kangguo Cheng ,  Shom S. Ponoth ,  Raghavasimhan Sreenivasan ,  Theodorus E. Standaert ,  Tenko Yamashita

    IPC: H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/66795 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/785

    Abstract: A robust gate spacer that can resist a long overetch that is required to form gate spacers in fin field effect transistors (FinFETs) and a method of forming the same are provided. The gate spacer includes a first gate spacer adjacent sidewalls of at least one hard mask and a top portion of sacrificial gate material of a sacrificial gate structure and a second gate spacer located beneath the first gate spacer and adjacent remaining portions of sidewalls of the sacrificial gate material. The first gate spacers is composed of a material having a high etch resistance that is not prone to material loss during subsequent exposure to dry or wet etch chemicals employed to form the second gate spacer and to remove the hard mask.

    Abstract translation: 提供了可以抵抗在鳍式场效应晶体管（FinFET）中形成栅极间隔物所需的长椭圆形的鲁棒栅极间隔物及其形成方法。 栅极间隔件包括邻近至少一个硬掩模的侧壁和牺牲栅极结构的牺牲栅极材料的顶部的第一栅极间隔件，以及位于第一栅极间隔物下方并且与牺牲栅极的侧壁的剩余部分相邻的第二栅极间隔物 材料。 第一栅极隔离物由具有高耐蚀刻性的材料组成，其在随后暴露于用于形成第二栅极间隔物的干法或湿蚀刻化学品中并且除去硬掩模之后不容易发生材料损失。

    FinFET semiconductor device having increased gate height control
    5.
    发明授权
    FinFET semiconductor device having increased gate height control 有权
    FinFET半导体器件具有增加的栅极高度控制

    公开(公告)号：US09059242B2

    公开(公告)日：2015-06-16

    申请号：US13685733

    申请日：2012-11-27

    Applicant: International Business Machines Corporation

    Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Shom Ponoth ,  Raghavasimhan Sreenivasan

    IPC: H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L21/84 ,  H01L29/66

    CPC classification number: H01L27/1211 ,  H01L21/76205 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/4238 ,  H01L29/6681 ,  H01L29/785

    Abstract: A semiconductor device includes a silicon-on-insulator (SOI) substrate having a buried oxide (BOX) layer, and a plurality of semiconductor fins formed on the BOX layer. The plurality of semiconductor fins include at least one pair of fins defining a BOX region therebetween. Gate lines are formed on the SOI substrate and extend across the plurality of semiconductor fins. Each gate line initially includes a dummy gate and a hardmask. A high dielectric (high-k) layer is formed on the hardmask and the BOX regions. At least one spacer is formed on each gate line such that the high-k layer is disposed between the spacer and the hardmask. A replacement gate process replaces the hardmask and the dummy gate with a metal gate. The high-k layer is ultimately removed from the gate line, while the high-k layer remains on the BOX region.

    Abstract translation: 半导体器件包括具有掩埋氧化物（BOX）层的绝缘体上硅（SOI）衬底和形成在BOX层上的多个半导体鳍片。 多个半导体鳍片包括限定其间的BOX区域的至少一对翅片。 栅极线形成在SOI衬底上并且跨越多个半导体鳍片延伸。 每个门线最初包括一个虚拟门和一个硬掩模。 在硬掩模和BOX区域上形成高电介质（高k）层。 在每个栅极线上形成至少一个间隔物，使得高k层位于间隔物和硬掩模之间。 替换门过程用金属门替代硬掩模和虚拟栅极。 高k层最终从栅极线去除，而高k层保留在BOX区域上。

    BACK-GATED SUBSTRATE AND SEMICONDUCTOR DEVICE, AND RELATED METHOD OF FABRICATION
    6.
    发明申请
    BACK-GATED SUBSTRATE AND SEMICONDUCTOR DEVICE, AND RELATED METHOD OF FABRICATION 有权
    后置基板和半导体器件，以及相关的制造方法

    公开(公告)号：US20140273418A1

    公开(公告)日：2014-09-18

    申请号：US13803856

    申请日：2013-03-14

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Kangguo Cheng ,  Thomas N. Adam ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan

    IPC: H01L21/02

    CPC classification number: H01L29/7831 ,  H01L21/7624 ,  H01L21/84 ,  H01L29/66484 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78648

    Abstract: A method of forming a semiconductor device is disclosed. The method includes forming a set of doped regions in a substrate; forming a crystalline dielectric layer on the substrate, the crystalline dielectric layer including an epitaxial oxide; forming a semiconductor layer on the crystalline dielectric layer, the semiconductor layer and the crystalline dielectric layer forming an extremely thin semiconductor-on-insulator (ETSOI) structure; and forming a set of devices on the semiconductor layer, wherein at least one device in the set of devices is formed over a doped region.

    Abstract translation: 公开了一种形成半导体器件的方法。 该方法包括在衬底中形成一组掺杂区域; 在所述衬底上形成结晶介电层，所述结晶介电层包括外延氧化物; 在所述结晶介质层上形成半导体层，所述半导体层和所述晶体介电层形成极薄的绝缘体上半导体（ETSOI）结构; 以及在所述半导体层上形成一组器件，其中所述器件组中的至少一个器件形成在掺杂区域上。

    SELF-ALIGNED BIOSENSORS WITH ENHANCED SENSITIVITY
    7.
    发明申请
    SELF-ALIGNED BIOSENSORS WITH ENHANCED SENSITIVITY 有权
    具有增强敏感性的自对准生物传感器

    公开(公告)号：US20140203332A1

    公开(公告)日：2014-07-24

    申请号：US13748197

    申请日：2013-01-23

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Raghavasimhan Sreenivasan ,  Sufi Zafar

    IPC: H01L29/66

    CPC classification number: H01L29/66 ,  G01N27/4145 ,  H01L29/66075

    Abstract: Non-planar semiconductor FET based sensors are provided that have an enhanced sensing area to volume ratio which results in faster response times than existing planar FET based sensors. The FET based sensors of the present disclosure include a V-shaped gate dielectric portion located in a V-shaped opening formed in a semiconductor substrate. In some embodiments, the FET based sensors of the present disclosure also include a self-aligned source region and a self-aligned drain region located in the semiconductor substrate and on opposing sides of the V-shaped opening. In other embodiments, the FET based sensors include a self-aligned source region and a self-aligned drain region located in the semiconductor substrate and on opposing sides of a gate dielectric material portion that is present on an uppermost surface of the semiconductor substrate.

    Abstract translation: 提供了基于非平面半导体FET的传感器，其具有增强的感测面积与体积比，其导致比现有的基于平面FET的传感器更快的响应时间。 本公开的基于FET的传感器包括位于形成在半导体衬底中的V形开口中的V形栅介质部分。 在一些实施例中，本公开的基于FET的传感器还包括位于半导体衬底中以及在V形开口的相对侧上的自对准源极区域和自对准漏极区域。 在其它实施例中，基于FET的传感器包括位于半导体衬底中的自对准源极区域和自对准漏极区域以及存在于半导体衬底的最上表面上的栅极电介质材料部分的相对侧。

    BORDERLESS CONTACTS FOR SEMICONDUCTOR TRANSISTORS
    8.
    发明申请
    BORDERLESS CONTACTS FOR SEMICONDUCTOR TRANSISTORS 有权
    半导体晶体管的无边界接触

    公开(公告)号：US20140162452A1

    公开(公告)日：2014-06-12

    申请号：US13709662

    申请日：2012-12-10

    Applicant: International Business Machines Corporation

    Inventor： Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek ,  Raghavasimhan Sreenivasan ,  Charan V. Surisetty ,  Thomas N. Adam

    IPC: H01L21/48

    CPC classification number: H01L21/486 ,  H01L21/76804 ,  H01L21/76897 ,  H01L29/78

    Abstract: Embodiments of the invention include methods of forming borderless contacts for semiconductor transistors. Embodiments may include providing a transistor structure including a gate, a spacer on a sidewall of the gate, a hard cap above the gate, a source/drain region adjacent to the spacer, and an interlevel dielectric layer around the gate, forming a contact hole above the source/drain region, forming a protective layer on portions of the hard cap and of the spacer exposed by the contact hole; deepening the contact hole by etching the interlevel dielectric layer while the spacer and the hard cap are protected by the protective layer, so that at least a portion of the source/drain region is exposed by the deepening of the contact hole; removing the protective layer; and forming a metal contact in the contact hole.

    Abstract translation: 本发明的实施例包括形成半导体晶体管的无边界触点的方法。 实施例可以包括提供晶体管结构，其包括栅极，栅极侧壁上的间隔物，栅极上方的硬帽，与间隔物相邻的源极/漏极区域以及围绕栅极的层间电介质层，形成接触孔 在源极/漏极区域上方形成在由接触孔暴露的硬盖和间隔物的部分上的保护层; 通过在衬垫和硬帽被保护层保护的同时蚀刻层间电介质层来加深接触孔，使得源/漏区的至少一部分通过接触孔的加深而暴露; 去除保护层; 并在接触孔中形成金属接触。

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