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公开(公告)号：US10388602B2
公开(公告)日：2019-08-20
申请号：US15251804
申请日：2016-08-30
发明人： Su Chen Fan , Vimal Kamineni , Andre P. Labonte , Ruilong Xie
IPC分类号： H01L21/768 , H01L23/528 , H01L23/532 , H01L23/535
摘要： A local interconnect structure includes a substrate having a dielectric layer and at least one semiconductor contact structure embedded in the dielectric layer. An electrically conductive material is deposited in a non-eroded contact trench that defines at least one electrically conducive contact via. The contact via extends from a first end that is flush with an upper surface of the dielectric layer to a second end that contacts the at one semiconductor contact structure. A local conductive material layer is formed in the dielectric layer and contacts the first end of the contact via. The non-eroded contact trench includes sharp upper corners formed at approximately ninety degrees with respect to the first end of the contact via.
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公开(公告)号：US10332977B2
公开(公告)日：2019-06-25
申请号：US15880059
申请日：2018-01-25
IPC分类号： H01L29/66 , H01L21/768 , H01L21/027 , H01L23/535 , H01L27/11 , H01L21/311 , H01L23/522 , H01L23/528
摘要： A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.
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公开(公告)号：US09953978B2
公开(公告)日：2018-04-24
申请号：US14981574
申请日：2015-12-28
发明人： Ruilong Xie , Kisik Choi , Su Chen Fan , Shom Ponoth
IPC分类号： H01L27/092 , H01L29/66 , H01L21/28 , H01L21/8238 , H01L29/40 , H01L29/49 , H01L29/423 , H01L29/51 , H01L29/78
CPC分类号： H01L27/0922 , H01L21/28114 , H01L21/823842 , H01L21/823864 , H01L27/092 , H01L29/401 , H01L29/42376 , H01L29/4958 , H01L29/4966 , H01L29/4983 , H01L29/517 , H01L29/66545 , H01L29/6656 , H01L29/78
摘要： A transistor device includes a gate structure positioned above a semiconductor substrate, and spaced-apart sidewall spacers positioned above the substrate and adjacent sidewalls of the gate structure. An internal sidewall surface of each of the spaced-apart sidewall spacers includes an upper sidewall surface portion and a lower sidewall surface portion positioned between the upper sidewall surface portion and a surface of the substrate, wherein a first lateral width between first upper ends of the upper sidewall surface portions is greater than a second lateral width between second upper ends of the lower sidewall surface portions.
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4.发明申请INTERCONNECT STRUCTURE INCLUDING MIDDLE OF LINE (MOL) METAL LAYER LOCAL INTERCONNECT ON ETCH STOP LAYER 有权互连结构，包括中间线（MOL）金属层局部互连在蚀刻停止层公开(公告)号：US20170018459A1
公开(公告)日：2017-01-19
申请号：US15277732
申请日：2016-09-27
发明人： Su Chen Fan , Sukwon Hong , William J. Taylor, JR.
IPC分类号： H01L21/768 , H01L23/528
CPC分类号： H01L23/535 , H01L21/76802 , H01L21/76829 , H01L21/7684 , H01L21/76843 , H01L21/76877 , H01L21/76895 , H01L23/528 , H01L23/53238 , H01L23/53295
摘要： An interconnect structure includes an insulator stack on an upper surface of a semiconductor substrate. The insulator stack includes a first insulator layer having at least one semiconductor device embedded therein and an etch stop layer interposed between the first insulator layer and a second insulator layer. At least one electrically conductive local contact extends through each of the second insulator layer, etch stop layer and, first insulator layer to contact the at least one semiconductor device. The interconnect structure further includes at least one first layer contact element disposed on the etch stop layer and against the at least one conductive local contact.
摘要翻译： 互连结构包括在半导体衬底的上表面上的绝缘体堆叠。 绝缘体堆叠包括具有嵌入其中的至少一个半导体器件的第一绝缘体层和插入在第一绝缘体层和第二绝缘体层之间的蚀刻停止层。 至少一个导电局部接触件延伸穿过第二绝缘体层，蚀刻停止层和与第一半导体器件接触的第一绝缘体层中的每一个。 所述互连结构还包括设置在所述蚀刻停止层上并抵靠所述至少一个导电性局部接触的至少一个第一层接触元件。
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5.发明申请FREESTANDING SPACER HAVING SUB-LITHOGRAPHIC LATERAL DIMENSION AND METHOD OF FORMING SAME 有权具有分层横向尺寸的自动间隔器及其形成方法公开(公告)号：US20160365425A1
公开(公告)日：2016-12-15
申请号：US14739662
申请日：2015-06-15
申请人： International Business Machines Corporation , Samsung Electronics Co., Ltd. , Globalfoundries Inc.
发明人： Hsueh-Chung Chen , Su Chen Fan , Dong Kwon Kim , Sean Lian , Fee Li Lie , Linus Jang
IPC分类号： H01L29/66 , H01L21/02 , H01L21/308 , H01L21/311
CPC分类号： H01L29/6653 , H01L21/02178 , H01L21/02181 , H01L21/02183 , H01L21/02186 , H01L21/3086 , H01L21/31116
摘要： An aspect of the invention includes a freestanding spacer having a sub-lithographic dimension for a sidewall image transfer process. The freestanding spacer comprises: a first spacer layer having a first portion disposed on the semiconductor layer; and a second spacer layer having a first surface disposed on the first portion of the first spacer layer, wherein the first spacer layer has a first dielectric constant and the second spacer layer has a second dielectric constant, the first dielectric constant being greater than the second dielectric constant, and wherein a dimension of each of the first and second spacer layers collectively determine the sub-lithographic lateral dimension of the freestanding spacer.
摘要翻译： 本发明的一个方面包括具有用于侧壁图像转印过程的亚光刻尺寸的独立间隔物。 独立间隔件包括：第一间隔层，其具有设置在半导体层上的第一部分; 以及第二间隔层，其具有设置在第一间隔层的第一部分上的第一表面，其中第一间隔层具有第一介电常数，第二间隔层具有第二介电常数，第一介电常数大于第二间隔层 介电常数，并且其中第一和第二间隔层中的每一个的尺寸共同确定独立间隔物的亚光刻横向尺寸。
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6.发明授权Methods of forming a combined gate and source/drain contact structure and the resulting device 有权形成组合的栅极和源极/漏极接触结构的方法以及所得到的器件公开(公告)号：US09455254B2
公开(公告)日：2016-09-27
申请号：US14536243
申请日：2014-11-07
IPC分类号： H01L21/8234 , H01L21/768 , H01L27/088 , H01L29/45 , H01L23/528 , H01L29/66 , H01L21/311 , H01L21/283 , H01L29/417
CPC分类号： H01L27/088 , H01L21/283 , H01L21/31144 , H01L21/76808 , H01L21/76834 , H01L21/76895 , H01L21/76897 , H01L21/823425 , H01L21/823437 , H01L21/823468 , H01L21/823475 , H01L23/528 , H01L29/41775 , H01L29/45 , H01L29/66515 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/66606 , H01L2924/0002 , H01L2924/00
摘要： One method disclosed herein includes, among other things, forming a gate cap layer above a recessed final gate structure and above recessed sidewall spacers, forming a recessed trench silicide region that is conductively coupled to the first source/drain region, the recessed trench silicide region having an upper surface that is positioned at a level that is below the recessed upper surface of the sidewall spacers, forming a combined contact opening in at least one layer of material that exposes a conductive portion of the recessed final gate structure and a portion of the trench silicide region, and forming a combined gate and source/drain contact structure in the combined contact opening.
摘要翻译： 本文公开的一种方法包括在凹陷的最终栅极结构上方和在凹陷的侧壁间隔物上方形成栅极盖层，形成导电耦合到第一源极/漏极区域的凹陷沟槽硅化物区域，凹陷沟槽硅化物区域 具有位于所述侧壁间隔物的凹陷的上表面下方的水平面的上表面，在暴露所述凹入的最终栅极结构的导电部分的至少一层材料中形成组合的接触开口， 沟槽硅化物区域，并且在组合的接触开口中形成组合的栅极和源极/漏极接触结构。
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公开(公告)号：US20180374932A1
公开(公告)日：2018-12-27
申请号：US16120870
申请日：2018-09-04
IPC分类号： H01L29/66 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/535 , H01L21/311 , H01L27/11 , H01L21/027
摘要： A gate tie-down structure includes a gate structure including a gate conductor and gate spacers and inner spacers formed on the gate spacers. Trench contacts are formed on sides of the gate structure. An interlevel dielectric (ILD) has a thickness formed over the gate structure. A horizontal connection is formed within the thickness of the ILD over an active area connecting the gate conductor and one of the trench contacts over one of the inner spacers.
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公开(公告)号：US09899259B2
公开(公告)日：2018-02-20
申请号：US15443523
申请日：2017-02-27
IPC分类号： H01L21/768 , H01L21/027 , H01L29/66 , H01L23/535 , H01L27/11 , H01L21/311 , H01L23/522 , H01L23/528
CPC分类号： H01L29/66553 , H01L21/0274 , H01L21/31111 , H01L21/76802 , H01L21/76805 , H01L21/7684 , H01L21/76877 , H01L21/76895 , H01L21/76897 , H01L23/5226 , H01L23/528 , H01L23/535 , H01L27/1104 , H01L29/665 , H01L29/66515 , H01L29/66545 , H01L29/6656 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.
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公开(公告)号：US20170278753A1
公开(公告)日：2017-09-28
申请号：US15618880
申请日：2017-06-09
IPC分类号： H01L21/768 , H01L27/11 , H01L29/66 , H01L23/535 , H01L21/027 , H01L21/311
CPC分类号： H01L29/66553 , H01L21/0274 , H01L21/31111 , H01L21/76802 , H01L21/76805 , H01L21/7684 , H01L21/76877 , H01L21/76895 , H01L21/76897 , H01L23/5226 , H01L23/528 , H01L23/535 , H01L27/1104 , H01L29/665 , H01L29/66515 , H01L29/66545 , H01L29/6656 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.
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公开(公告)号：US20170162438A1
公开(公告)日：2017-06-08
申请号：US15432372
申请日：2017-02-14
IPC分类号： H01L21/768 , H01L27/11 , H01L29/66 , H01L23/522 , H01L23/528
CPC分类号： H01L29/66553 , H01L21/0274 , H01L21/31111 , H01L21/76802 , H01L21/76805 , H01L21/7684 , H01L21/76877 , H01L21/76895 , H01L21/76897 , H01L23/5226 , H01L23/528 , H01L23/535 , H01L27/1104 , H01L29/665 , H01L29/66515 , H01L29/66545 , H01L29/6656 , H01L2924/0002 , H01L2924/00
摘要： A gate tie-down structure includes a gate structure including a gate conductor and gate spacers and inner spacers formed on the gate spacers. Trench contacts are formed on sides of the gate structure. An interlevel dielectric (ILD) has a thickness formed over the gate structure. A horizontal connection is formed within the thickness of the ILD over an active area connecting the gate conductor and one of the trench contacts over one of the inner spacers.
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