公开(公告)号：US08941156B2

公开(公告)日：2015-01-27

申请号：US13735315

申请日：2013-01-07

申请人： International Business Machines Corporation ,  GlobalFoundries, Inc.

发明人： Marc Adam Bergendahl ,  Kangguo Cheng ,  David Vaclav Horak ,  Ali Khakifirooz ,  Shom Ponoth ,  Theodorus Eduardus Standaert ,  Chih-Chao Yang ,  Charles William Koburger, III ,  Xiuyu Cai ,  Ruilong Xie

IPC分类号： H01L29/78

CPC分类号： H01L27/0886 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/7855

摘要： Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed.

摘要翻译： 本发明的实施例提供一种形成半导体结构的方法。 该方法包括在衬底的顶部上形成一组器件特征; 在所述组装置特征的顶部直接形成第一介电层，并在所述基板的顶部上形成第一电介质层，从而产生从所述基板的顶表面测量的所述第一电介质层的高度分布，所述高度分布与所述基板的图案相关联 完全围绕设备特征的绝缘结构; 以及在由所述图案限定的区域中形成第二电介质层以形成所述绝缘结构。 还公开了通过该方法形成的结构。

公开(公告)号：US20140191319A1

公开(公告)日：2014-07-10

申请号：US13733943

申请日：2013-01-04

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

发明人： Kangguo Cheng ,  Shom Ponoth ,  Balasubramanian Pranatharthiharan ,  Theodorus Eduardus Standaert ,  Tenko Yamashita ,  Robert J. Miller

IPC分类号： H01L29/78 ,  H01L21/02

CPC分类号： H01L21/845 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/1211 ,  H01L29/861

摘要： A diode for integration with finFET devices is disclosed. An in-situ doped epitaxial silicon region is grown on the cathode or anode of the diode to increase the surface area of the junction and overall silicon volume for improved heat dissipation during an ESD event.

摘要翻译： 公开了一种用于与finFET器件集成的二极管。 在二极管的阴极或阳极上生长原位掺杂的外延硅区域，以增加结的表面面积和整体硅体积，以改善ESD事件期间的散热。

公开(公告)号：US20150061040A1

公开(公告)日：2015-03-05

申请号：US14538401

申请日：2014-11-11

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

发明人： Marc Adam Bergendahl ,  Kangguo Cheng ,  David Vaclav Horak ,  Ali Khakifirooz ,  Shom Ponoth ,  Theodorus Eduardus Standaert ,  Chih-Chao Yang ,  Charles William Koburger, III ,  Xiuyu Cai ,  Ruilong Xie

IPC分类号： H01L27/088 ,  H01L29/06

CPC分类号： H01L27/0886 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/7855

摘要： Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed.

摘要翻译： 本发明的实施例提供一种形成半导体结构的方法。 该方法包括在衬底的顶部上形成一组器件特征; 在所述组装置特征的顶部直接形成第一介电层，并在所述基板的顶部上形成第一电介质层，从而产生从所述基板的顶表面测量的所述第一电介质层的高度分布，所述高度分布与所述基板的图案相关联 完全围绕设备特征的绝缘结构; 以及在由所述图案限定的区域中形成第二电介质层以形成所述绝缘结构。 还公开了通过该方法形成的结构。

公开(公告)号：US20140191296A1

公开(公告)日：2014-07-10

申请号：US13735315

申请日：2013-01-07

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

发明人： Marc Adam Bergendahl ,  Kangguo Cheng ,  David Vaclav Horak ,  Ali Khakifirooz ,  Shom Ponoth ,  Theodorus Eduardus Standaert ,  Chih-Chao Yang ,  Charles William Koburger, III ,  Xiuyu Cai ,  Ruilong Xie

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L27/0886 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/7855

摘要： Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed.

摘要翻译： 本发明的实施例提供一种形成半导体结构的方法。 该方法包括在衬底的顶部上形成一组器件特征; 在所述一组装置特征的顶部直接形成第一介电层，并且在所述基板的顶部上形成第一电介质层，从而产生从所述基板的顶表面测量的所述第一介电层的高度分布，所述高度分布与所述基板的图案相关联 完全围绕设备特征的绝缘结构; 以及在由所述图案限定的区域中形成第二电介质层以形成所述绝缘结构。 还公开了通过该方法形成的结构。

公开(公告)号：US09349838B2

公开(公告)日：2016-05-24

申请号：US14530034

申请日：2014-10-31

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Balasubramanian Pranatharthi Haran ,  Junjun Li ,  Shom Ponoth ,  Theodorus Eduardus Standaert ,  Tenko Yamashita

IPC分类号： H01L29/66 ,  H01L29/861 ,  H01L29/40 ,  H01L29/423 ,  H01L27/02 ,  H01L23/367 ,  H01L23/373 ,  H01L29/06 ,  H01L27/12

CPC分类号： H01L29/66795 ,  H01L23/367 ,  H01L23/3738 ,  H01L27/0255 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0603 ,  H01L29/402 ,  H01L29/423 ,  H01L29/42376 ,  H01L29/6609 ,  H01L29/66742 ,  H01L29/861 ,  H01L29/8613 ,  H01L2924/0002 ,  H01L2924/00

摘要： Diodes and resistors for integrated circuits are provided. Deep trenches (DTs) are integrated into the diodes and resistors for the purposes of thermal conduction. The deep trenches facilitate conduction of heat from a semiconductor-on-insulator substrate to a bulk substrate. Semiconductor fins may be formed to align with the deep trenches.

公开(公告)号：US20160064330A1

公开(公告)日：2016-03-03

申请号：US14883972

申请日：2015-10-15

申请人： International Business Machines Corporation

发明人： Elbert Emin Huang ,  Takeshi Nogami ,  Raghuveer R. Patlolla ,  Christopher J. Penny ,  Theodorus Eduardus Standaert

IPC分类号： H01L23/532 ,  H01L23/522

CPC分类号： H01L23/528 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the present invention provide increased distance between vias and neighboring metal lines in a back end of line (BEOL) structure. A copper alloy seed layer is deposited in trenches that are formed in a dielectric layer. The trenches are then filled with copper. An anneal is then performed to create a self-forming barrier using a seed layer constituent, such as manganese, as the manganese is drawn to the dielectric layer during the anneal. The self-forming barrier is disposed on a shoulder region of the dielectric layer, increasing the effective distance between the via and its neighboring metal lines.

摘要翻译： 本发明的实施例提供了在后端（BEOL）结构中的通孔和相邻金属线之间的距离增加。 铜合金种子层沉积在形成在电介质层中的沟槽中。 然后用铜填充沟槽。 然后，在退火期间，当锰在介电层中被拉出时，进行退火以形成使用诸如锰的种子层成分的自形成势垒。 自形成障碍物设置在电介质层的肩部区域上，增加了通孔及其相邻金属线之间的有效距离。

公开(公告)号：US20140284717A1

公开(公告)日：2014-09-25

申请号：US13849694

申请日：2013-03-25

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Theodorus Eduardus Standaert ,  Kangguo Cheng ,  Junjun Li ,  Balasubramanian Pranatharthi Haran ,  Shom Ponoth ,  Tenko Yamashita

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L23/367 ,  H01L23/3738 ,  H01L27/0255 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0603 ,  H01L29/402 ,  H01L29/423 ,  H01L29/42376 ,  H01L29/6609 ,  H01L29/66742 ,  H01L29/861 ,  H01L29/8613 ,  H01L2924/0002 ,  H01L2924/00

摘要： Diodes and resistors for integrated circuits are provided. Deep trenches (DTs) are integrated into the diodes and resistors for the purposes of thermal conduction. The deep trenches facilitate conduction of heat from a semiconductor-on-insulator substrate to a bulk substrate. Semiconductor fins may be formed to align with the deep trenches.

摘要翻译： 提供用于集成电路的二极管和电阻。 深沟槽（DT）集成到二极管和电阻器中，用于热传导。 深沟槽促进热从绝缘体上半导体衬底传导到体衬底。 半导体散热片可形成为与深沟槽对齐。

公开(公告)号：US20180114723A1

公开(公告)日：2018-04-26

申请号：US15335122

申请日：2016-10-26

申请人： International Business Machines Corporation

发明人： Benjamin David Briggs ,  Joe Lee ,  Theodorus Eduardus Standaert

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L21/76831 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53238

摘要： A method of forming fully aligned vias in a semiconductor device includes forming an Mx level interconnect line embedded in an Mx interlevel dielectric (ILD). The Mx level interconnect is recessed below the Mx interlevel dielectric or a dielectric is selectively deposited on the Mx interlevel dielectric. The method also includes laterally etching the exposed upper portion of the Mx interlevel dielectric bounding the recess or laterally etching the selectively deposited dielectric. A dielectric cap layer and an Mx+1 level interlevel dielectric is deposited on top of the Mx interlevel dielectric, and a via opening is formed.

公开(公告)号：US09252242B2

公开(公告)日：2016-02-02

申请号：US13849694

申请日：2013-03-25

申请人： International Business Machines Corporation

发明人： Theodorus Eduardus Standaert ,  Kangguo Cheng ,  Junjun Li ,  Balasubramanian Pranatharthi Haran ,  Shom Ponoth ,  Tenko Yamashita

IPC分类号： H01L29/66 ,  H01L29/861 ,  H01L29/40 ,  H01L29/423 ,  H01L27/02 ,  H01L23/367 ,  H01L23/373 ,  H01L29/06 ,  H01L27/12

CPC分类号： H01L29/66795 ,  H01L23/367 ,  H01L23/3738 ,  H01L27/0255 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0603 ,  H01L29/402 ,  H01L29/423 ,  H01L29/42376 ,  H01L29/6609 ,  H01L29/66742 ,  H01L29/861 ,  H01L29/8613 ,  H01L2924/0002 ,  H01L2924/00

摘要： Diodes and resistors for integrated circuits are provided. Deep trenches (DTs) are integrated into the diodes and resistors for the purposes of thermal conduction. The deep trenches facilitate conduction of heat from a semiconductor-on-insulator substrate to a bulk substrate. Semiconductor fins may be formed to align with the deep trenches.

摘要翻译： 提供用于集成电路的二极管和电阻。 深沟槽（DT）集成到二极管和电阻器中，用于热传导。 深沟槽促进热从绝缘体上半导体衬底传导到体衬底。 半导体散热片可形成为与深沟槽对齐。

公开(公告)号：US20150340288A1

公开(公告)日：2015-11-26

申请号：US14529825

申请日：2014-10-31

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus Eduardus Standaert ,  Tenko Yamashita

IPC分类号： H01L21/8234 ,  H01L21/02 ,  H01L21/308

CPC分类号： H01L27/10826 ,  H01L21/76224 ,  H01L21/76243 ,  H01L21/76283 ,  H01L21/845 ,  H01L27/1211

摘要： An improved finFET and method of fabrication using a silicon-on-nothing process flow is disclosed. Nitride spacers protect the fin sides during formation of cavities underneath the fins for the silicon-on-nothing (SON) process. A flowable oxide fills the cavities to form an insulating dielectric layer under the fins.

摘要翻译： 公开了一种改进的finFET和使用无硅无工艺流程的制造方法。 氮化物间隔件在形成用于无硅无机（SON）工艺的翅片下方的空腔的形成期间保护翅片侧面。 可流动氧化物填充空腔以在翅片下形成绝缘介电层。