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公开(公告)号：US11195929B2
公开(公告)日：2021-12-07
申请号：US16668473
申请日：2019-10-30
发明人： Takashi Ando , Ruqiang Bao , Masanobu Hatanaka , Vijay Narayanan , Yohei Ogawa , John Rozen
IPC分类号： H01L29/49 , H01L29/43 , H01L27/092 , H01L21/285 , H01L21/28 , H01L21/8238 , H01L29/423 , H01L29/66 , B82Y10/00 , H01L29/40 , H01L29/78 , H01L29/06 , H01L29/775
摘要： A gate structure for effective work function adjustments of semiconductor devices that includes a gate dielectric on a channel region of a semiconductor device; a first metal nitride in direct contact with the gate dielectric; a conformal carbide of Aluminum material layer having an aluminum content greater than 30 atomic wt. %; and a second metal nitride layer in direct contact with the conformal aluminum (Al) and carbon (C) containing material layer. The conformal carbide of aluminum (Al) layer includes aluminum carbide, or Al4C3, yielding an aluminum (Al) content up to 57 atomic % (at. %) and work function setting from 3.9 eV to 5.0 eV at thicknesses below 25 Å. Such structures can present metal gate length scaling and resistance benefit below 25 nm compared to state of the art work function electrodes.
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公开(公告)号：US10283610B2
公开(公告)日：2019-05-07
申请号：US15894246
申请日：2018-02-12
发明人： Vijay Narayanan , Yohei Ogawa , John Rozen
IPC分类号： H01L29/51 , H01L29/423 , H01L21/28 , H01L29/78 , H01L29/20 , H01L29/66 , H01L21/02 , H01L21/306 , H01L29/06
摘要： A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.
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公开(公告)号：US09984940B1
公开(公告)日：2018-05-29
申请号：US15418916
申请日：2017-01-30
发明人： Jack O. Chu , Stephen M. Gates , Masanobu Hatanaka , Vijay Narayanan , Deborah A. Neumayer , Yohei Ogawa , John Rozen
CPC分类号： H01L21/845 , H01L21/02178 , H01L21/0228 , H01L21/02304 , H01L21/28008 , H01L21/28158 , H01L21/28255 , H01L21/28264 , H01L23/298 , H01L23/3171 , H01L23/3192 , H01L27/1211 , H01L29/785
摘要： A scaled dielectric stack interlayer, compatible with subsequent high temperature processing with good electrical transport & reliability properties is provided. A method for forming a conformal aSi:H passivation layer on a semiconductor device is described. A patterned semiconductor wafer is placed in in a process chamber with a first layer formed thereon and a second layer formed thereon, the first layer and the second layer being two different materials Next, a SixH(2x+2) based deposition up to a temperature of 400 degrees Celsius is used on the first layer and the second layer thereby forming a conformal aSi:H passivating layer is formed at a higher rate of deposition on the first layer selectively and a lower rate of deposit on the second layer.
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公开(公告)号：US10529815B2
公开(公告)日：2020-01-07
申请号：US15799231
申请日：2017-10-31
发明人： Takashi Ando , Ruqiang Bao , Masanobu Hatanaka , Vijay Narayanan , Yohei Ogawa , John Rozen
IPC分类号： H01L29/43 , H01L29/49 , H01L27/092 , H01L21/285 , H01L21/28 , H01L21/8238 , H01L29/66 , B82Y10/00 , H01L29/40 , H01L29/423 , H01L29/78 , H01L29/775 , H01L29/06
摘要： A gate structure for effective work function adjustments of semiconductor devices that includes a gate dielectric on a channel region of a semiconductor device; a first metal nitride in direct contact with the gate dielectric; a conformal carbide of Aluminum material layer having an aluminum content greater than 30 atomic wt. %; and a second metal nitride layer in direct contact with the conformal aluminum (Al) and carbon (C) containing material layer. The conformal carbide of aluminum (Al) layer includes aluminum carbide, or Al4C3, yielding an aluminum (Al) content up to 57 atomic % (at. %) and work function setting from 3.9 eV to 5.0 eV at thicknesses below 25 Å. Such structures can present metal gate length scaling and resistance benefit below 25 nm compared to state of the art work function electrodes.
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公开(公告)号：US09984870B2
公开(公告)日：2018-05-29
申请号：US15198537
申请日：2016-06-30
发明人： Takashi Ando , Vijay Narayanan , Yohei Ogawa , John Rozen
IPC分类号： H01L21/02
CPC分类号： H01L21/02304 , H01L21/02178 , H01L21/02181 , H01L21/02274 , H01L21/0228 , H01L21/02301
摘要： A technique relates to in-situ cleaning of a high-mobility substrate. Alternating pulses of a metal precursor and exposure to a plasma of a gas or gas mixture are applied. The gas or gas mixture contains both nitrogen and hydrogen (e.g., NH3). A passivation layer is formed on the high-mobility substrate by alternating pulses of the metal precursor and exposure to the plasma of a gas, or gas mixture, containing both nitrogen and hydrogen.
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公开(公告)号：US09972695B2
公开(公告)日：2018-05-15
申请号：US15228160
申请日：2016-08-04
发明人： Vijay Narayanan , Yohei Ogawa , John Rozen
IPC分类号： H01L29/51 , H01L21/306 , H01L21/02 , H01L29/66 , H01L29/20 , H01L29/78 , H01L21/28 , H01L29/423 , H01L29/06
CPC分类号： H01L29/513 , H01L21/02043 , H01L21/02178 , H01L21/02186 , H01L21/02194 , H01L21/02205 , H01L21/02241 , H01L21/02274 , H01L21/0228 , H01L21/02307 , H01L21/28264 , H01L21/30612 , H01L29/0669 , H01L29/20 , H01L29/42364 , H01L29/517 , H01L29/518 , H01L29/66522 , H01L29/66545 , H01L29/66575 , H01L29/78 , H01L29/7827 , H01L29/7851
摘要： A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.
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公开(公告)号：US10217834B2
公开(公告)日：2019-02-26
申请号：US15684263
申请日：2017-08-23
发明人： Vijay Narayanan , Yohei Ogawa , John Rozen
IPC分类号： H01L29/51 , H01L29/423 , H01L21/28 , H01L29/20 , H01L29/66 , H01L21/02 , H01L21/306 , H01L29/06 , H01L29/78
摘要： A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.
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公开(公告)号：US20180040710A1
公开(公告)日：2018-02-08
申请号：US15684498
申请日：2017-08-23
发明人： Vijay Narayanan , Yohei Ogawa , John Rozen
IPC分类号： H01L29/51 , H01L21/02 , H01L29/78 , H01L29/423 , H01L29/20 , H01L21/28 , H01L21/306 , H01L29/66 , H01L29/06
CPC分类号： H01L29/513 , H01L21/02043 , H01L21/02178 , H01L21/02186 , H01L21/02194 , H01L21/02205 , H01L21/02241 , H01L21/02274 , H01L21/0228 , H01L21/02307 , H01L21/28264 , H01L21/30612 , H01L29/0669 , H01L29/20 , H01L29/42364 , H01L29/517 , H01L29/518 , H01L29/66522 , H01L29/66545 , H01L29/66575 , H01L29/78 , H01L29/7827 , H01L29/7851
摘要： A method of forming a gate stack that includes treating a semiconductor substrate with a wet etch chemistry to clean a surface of the semiconductor substrate and form an oxide containing interfacial layer, and converting the oxide containing interfacial layer to a binary alloy oxide based interlayer using a plasma deposition sequence including alternating a metal gas precursor and a nitrogen and/or hydrogen containing plasma. The method of forming the gate stack may further include forming a high-k dielectric layer atop the binary alloy oxide based interlayer.
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公开(公告)号：US20200066859A1
公开(公告)日：2020-02-27
申请号：US16668473
申请日：2019-10-30
发明人： Takashi Ando , Ruqiang Bao , Masanobu Hatanaka , Vijay Narayanan , Yohei Ogawa , John Rozen
IPC分类号： H01L29/43 , H01L29/49 , H01L27/092 , H01L21/285 , H01L21/28 , H01L21/8238 , H01L29/423 , H01L29/66 , B82Y10/00 , H01L29/40
摘要： A gate structure for effective work function adjustments of semiconductor devices that includes a gate dielectric on a channel region of a semiconductor device; a first metal nitride in direct contact with the gate dielectric; a conformal carbide of Aluminum material layer having an aluminum content greater than 30 atomic wt. %; and a second metal nitride layer in direct contact with the conformal aluminum (Al) and carbon (C) containing material layer. The conformal carbide of aluminum (Al) layer includes aluminum carbide, or Al4C3, yielding an aluminum (Al) content up to 57 atomic % (at. %) and work function setting from 3.9 eV to 5.0 eV at thicknesses below 25 Å. Such structures can present metal gate length scaling and resistance benefit below 25 nm compared to state of the art work function electrodes.
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公开(公告)号：US20190131418A1
公开(公告)日：2019-05-02
申请号：US15799231
申请日：2017-10-31
发明人： Takashi Ando , Ruqiang Bao , Masanobu Hatanaka , Vijay Narayanan , Yohei Ogawa , John Rozen
IPC分类号： H01L29/43 , H01L29/49 , H01L21/28 , H01L21/285 , H01L27/092
摘要： A gate structure for effective work function adjustments of semiconductor devices that includes a gate dielectric on a channel region of a semiconductor device; a first metal nitride in direct contact with the gate dielectric; a conformal carbide of Aluminum material layer having an aluminum content greater than 30 atomic wt. %; and a second metal nitride layer in direct contact with the conformal aluminum (Al) and carbon (C) containing material layer. The conformal carbide of aluminum (Al) layer includes aluminum carbide, or Al4C3, yielding an aluminum (Al) content up to 57 atomic % (at. %) and work function setting from 3.9 eV to 5.0 eV at thicknesses below 25 Å. Such structures can present metal gate length scaling and resistance benefit below 25 nm compared to state of the art work function electrodes.
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