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    Packing density for flash memories
    3.
    发明授权
    Packing density for flash memories 失效
    闪存的包装密度

    公开(公告)号：US5622881A

    公开(公告)日：1997-04-22

    申请号：US319393

    申请日：1994-10-06

    申请人： Joyce E. Acocella ,  Carol Galli ,  Louis Lu-Chen Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph F. Shepard

    发明人： Joyce E. Acocella ,  Carol Galli ,  Louis Lu-Chen Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph F. Shepard

    IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C13/00

    CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11546 ,  Y10S148/117 ,  Y10S438/981

    摘要： Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.

    摘要翻译： 通过将浮置栅极结构限制在被薄氮化物层覆盖的隔离结构之间，可在电可编程存储器中实现提高的封装密度以及改进的性能和制造产量。 浮栅的限制是通过平面化，优选采用自限制化学/机械抛光工艺，覆盖覆盖隔离结构的氮化物层的表面来实现的。 然后可以在基本平坦的表面上形成栅极氧化物和控制电极连接，而不会损害器件必须承受编程的栅极氧化物的质量或击穿电压。 由于避免了形成这些连接的严格的拓扑结构，所以可能包括可能包括金属连接的低电阻连接的形成得到改进，并且允许将存储器单元的晶体管缩放到先前不可能的尺寸。

    Method of forming integrated interconnect for very high density DRAMs
    4.
    发明授权
    Method of forming integrated interconnect for very high density DRAMs 失效
    形成非常高密度DRAM的集成互连的方法

    公开(公告)号：US5389559A

    公开(公告)日：1995-02-14

    申请号：US161763

    申请日：1993-12-02

    申请人： Chang-Ming Hsieh ,  Louis L. Hsu ,  Toshio Mii ,  Seiki Ogura ,  Joseph F. Shepard

    发明人： Chang-Ming Hsieh ,  Louis L. Hsu ,  Toshio Mii ,  Seiki Ogura ,  Joseph F. Shepard

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L27/10861 ,  H01L27/10829

    摘要： A trench capacitor DRAM cell with Shallow Trench Isolation (STI), a self-aligned buried strap and the method of making the cell. A trench capacitor is defined in a substrate. The trench capacitor's polysilicon (poly) plate is recessed below the surface of the substrate and the trench sidewalls are exposed above the poly. A doped poly layer is deposited over the surface contacting both the sidewall and the trench capacitor's poly plate. Horizontal portions of the poly layer are removed either through chemmech polishing or Reactive Ion Etching (RIE). A shallow trench is formed, removing one formerly exposed trench sidewall and a portion of the trench capacitor's poly plate in order to isolate the DRAM cell from adjacent cells. The remaining poly strap, along the trench sidewall contacting the poly plate, is self aligned to contact the source of the DRAM Pass gate Field Effect Transistor (FET). After the shallow trench is filled with oxide, FET's are formed on the substrate, completing the cell. In an alternate embodiment, instead of recessing the poly plate, a shallow trench is formed spanning the entire width of the trench capacitor. The deposited polysilicon is selectively removed, having straps that strap the poly plate to the shallow trench sidewall.

    摘要翻译： 具有浅沟槽隔离（STI）的沟槽电容器DRAM单元，自对准掩埋带和制造电池的方法。 沟槽电容器限定在衬底中。 沟槽电容器的多晶硅（poly）板在衬底的表面下方凹入，并且沟槽侧壁暴露在聚合物上方。 在与侧壁和沟槽电容器的多晶硅板接触的表面上沉积掺杂的多晶硅层。 通过化学抛光或反应离子蚀刻（RIE）去除多层的水平部分。 形成浅沟槽，去除一个以前暴露的沟槽侧壁和沟槽电容器的多晶片的一部分，以便将DRAM单元与相邻单元隔离。 沿着与多晶硅板接触的沟槽侧壁的剩余多晶带自对准以接触DRAM通过栅极场效应晶体管（FET）的源极。 在浅沟槽充满氧化物之后，在衬底上形成FET，从而完成电池。 在替代实施例中，代替凹陷多晶硅，形成跨越沟槽电容器的整个宽度的浅沟槽。 选择性地去除沉积的多晶硅，具有将多晶板绑定到浅沟槽侧壁的带。

    Method for forming a DRAM trench cell capacitor having a strap connection
    5.
    发明授权
    Method for forming a DRAM trench cell capacitor having a strap connection 失效
    用于形成具有带连接的DRAM沟槽电池电容器的方法

    公开(公告)号：US5384277A

    公开(公告)日：1995-01-24

    申请号：US169875

    申请日：1993-12-17

    申请人： Louis L. Hsu ,  Toshio Mii ,  Joseph F. Shepard ,  Seiki Ogura

    发明人： Louis L. Hsu ,  Toshio Mii ,  Joseph F. Shepard ,  Seiki Ogura

    IPC分类号： H01L21/285 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

    CPC分类号： H01L21/28525 ,  H01L27/10829

    摘要： A method of forming a MOS DRAM cell having a trench capacitor in which the strap connection to the trench capacitor, the source, drain, and isolation are all raised above the surface of the single crystal silicon includes the steps of forming the trench capacitors, depositing a blanket gate stack including the gate oxide and a set of gate layers, and then depositing isolation members in apertures etched in the gate stack using the gate oxide as an etch stop. The same sidewalls that are used to form an LDD source and drain combine with nitride sidewalls on a gate contact aperture to separate a gate contact from source and drain contacts.

    摘要翻译： 一种形成具有沟槽电容器的MOS DRAM单元的方法，其中与沟槽电容器的带连接，源极，漏极和隔离都在单晶硅的表面上方升高，包括以下步骤：形成沟槽电容器， 包括栅极氧化物和一组栅极层的覆盖栅极堆叠，然后使用栅极氧化物作为蚀刻停止层，在隔离栅堆叠中蚀刻的孔中沉积隔离元件。 用于形成LDD源极和漏极的相同侧壁与栅极接触孔上的氮化物侧壁结合，以将栅极接触与源极和漏极接触分开。

    Vertical dual gate thin film transistor with self-aligned gates / offset drain
    6.
    发明授权
    Vertical dual gate thin film transistor with self-aligned gates / offset drain 失效
    具有自对准栅极/漏极漏极的垂直双栅极薄膜晶体管

    公开(公告)号：US5574294A

    公开(公告)日：1996-11-12

    申请号：US576103

    申请日：1995-12-22

    申请人： Joseph F. Shepard

    发明人： Joseph F. Shepard

    IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L29/76 ,  H01L21/265

    CPC分类号： H01L29/6675 ,  H01L29/78618 ,  H01L29/78624 ,  H01L29/78642 ,  H01L29/78648

    摘要： A process for making a dual gated thin film transistor (TFT), having a sidewall channel and self-aligned gates and off-set drain is disclosed. A substrate having a top surface with insulating regions is provided. A bilayer having a polysilicon bottom layer and an insulating top layer, is patterned to form the bottom electrode of the TFT with an insulating layer over it. A first gate insulator is formed in contact with sides of the bottom electrode. A layer of second polysilicon having two end source and drain regions and a middle channel region is formed with the channel region being vertical along the side of the bottom electrode and overlying insulator layer and in contact with the first gate insulator. A second gate insulator is formed on the second polysilicon. A contact opening is etched in the insulating layers overlying the bottom electrode, in a region away from the second polysilicon to expose surface of part of the bottom electrode. A third polysilicon layer is deposited and patterned to have a horizontal region overlapping the contact opening to make contact to the bottom electrode, and to have sidewall electrode regions in contact with the second gate insulator and superadjacent to the channel region act as the top electrode of the TFT. The sidewall spacer electrode regions are connected to the horizontal regions of the third polysilicon. Thus the top and bottom electrode are also electrically connected together. The source and drain regions are doped selectively. By choice of implant conditions, the off-set region having a desired dopant concentration different from the device layer concentration, can be formed at the drain side of the dual gated TFT.

    摘要翻译： 公开了一种制造具有侧壁通道和自对准栅极和偏置漏极的双门控薄膜晶体管（TFT）的工艺。 提供了具有绝缘区域的顶面的基板。 将具有多晶硅底层和绝缘顶层的双层图案化以形成TFT上的绝缘层的TFT的底部电极。 第一栅极绝缘体形成为与底部电极的侧面接触。 形成具有两个端部源极和漏极区域以及中间沟道区域的第二多晶硅层，其中沟道区域沿着底部电极和上部绝缘体层的侧面是垂直的并且与第一栅极绝缘体接触。 在第二多晶硅上形成第二栅极绝缘体。 在覆盖底部电极的绝缘层中，在远离第二多晶硅的区域中蚀刻接触开口以暴露底部电极的一部分的表面。 第三多晶硅层被沉积和图案化以具有与接触开口重叠的水平区域以与底部电极接触，并且具有与第二栅极绝缘体接触并且与沟道区域相邻的侧壁电极区域用作顶部电极 TFT。 侧壁间隔电极区域连接到第三多晶硅的水平区域。 因此，顶部和底部电极也电连接在一起。 源区和漏区被选择性掺杂。 通过选择注入条件，可以在双门控TFT的漏极侧形成具有不同于器件层浓度的期望掺杂剂浓度的偏移区域。

    DRAM cell having raised source, drain and isolation
    7.
    发明授权
    DRAM cell having raised source, drain and isolation 失效
    DRAM电池具有升高的源极，漏极和隔离

    公开(公告)号：US5369049A

    公开(公告)日：1994-11-29

    申请号：US169873

    申请日：1993-12-17

    申请人： Joyce E. Acocella ,  Louis L. Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph F. Shepard

    发明人： Joyce E. Acocella ,  Louis L. Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph F. Shepard

    IPC分类号： H01L27/108 ,  H01L27/00 ,  H01L21/70

    CPC分类号： H01L27/10829

    摘要： A method of forming a MOS DRAM cell having a trench capacitor in which the strap connection to the trench capacitor, the source, drain, and isolation are all raised above the surface of the single crystal silicon includes the steps of forming the trench capacitors, depositing a blanket gate stack including the gate oxide and a set of gate layers, and then depositing isolation members in apertures etched in the gate stack using the gate oxide as an etch stop. The same sidewalls that are used to form an LDD source and drain form a self-aligned aperture for a surface strap that insulates the strap from misaligned portions of the gate stack.

    摘要翻译： 一种形成具有沟槽电容器的MOS DRAM单元的方法，其中与沟槽电容器的带连接，源极，漏极和隔离都在单晶硅的表面上方升高，包括以下步骤：形成沟槽电容器， 包括栅极氧化物和一组栅极层的覆盖栅极堆叠，然后使用栅极氧化物作为蚀刻停止层，在隔离栅堆叠中蚀刻的孔中沉积隔离元件。 用于形成LDD源和漏极的相同侧壁形成用于将带与栅堆叠的未对准部分绝缘的表面带的自对准孔。

    Method of making a DRAM cell with trench capacitor
    9.
    发明授权
    Method of making a DRAM cell with trench capacitor 失效
    制造具有沟槽电容器的DRAM单元的方法

    公开(公告)号：US5395786A

    公开(公告)日：1995-03-07

    申请号：US269852

    申请日：1994-06-30

    申请人： Louis L. Hsu ,  Sieki Ogura ,  Joseph F. Shepard

    发明人： Louis L. Hsu ,  Sieki Ogura ,  Joseph F. Shepard

    IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70

    CPC分类号： H01L27/10861

    摘要： A DRAM cell of the trench capacitor type is formed by a simplified process that reduces cost and increases process latitude by forming the trench collar in a single step of expanding a shallow trench horizontally and conformally coating the collar; etching the trench to its final depth and implanting the bottom heavily and doping the walls lightly; recessing the poly liner in a non-critical step that exposes a contact area between the top of the poly and the adjacent transistor electrode.

    摘要翻译： 沟槽电容器类型的DRAM单元通过简化的工艺形成，该工艺通过在使水平并且适形地涂覆套环的单个步骤中形成沟槽套圈来降低成本并增加工艺的纬度; 将沟槽蚀刻到其最终深度并且重要地注入底部并轻轻掺杂壁; 在暴露多晶硅和相邻晶体管电极的顶部之间的接触面积的非关键步骤中使多层衬垫凹陷。

    Semiconductor device and wafer structure having a planar buried interconnect by wafer bonding
    10.
    发明授权
    Semiconductor device and wafer structure having a planar buried interconnect by wafer bonding 失效
    半导体器件和晶片结构通过晶片接合具有平面埋入互连

    公开(公告)号：US5382832A

    公开(公告)日：1995-01-17

    申请号：US131344

    申请日：1993-10-04

    申请人： Taqi N. Buti ,  Louis L. Hsu ,  Rajiv V. Joshi ,  Joseph F. Shepard

    发明人： Taqi N. Buti ,  Louis L. Hsu ,  Rajiv V. Joshi ,  Joseph F. Shepard

    IPC分类号： H01L21/3205 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/98 ,  H01L23/522 ,  H01L27/04 ,  H01L23/48 ,  H01L27/01

    CPC分类号： H01L25/50 ,  H01L21/743 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76283 ,  H01L2924/0002 ,  Y10S148/012 ,  Y10S148/135 ,  Y10S438/977

    摘要： A wafer structure suitable for the formation of semiconductor devices thereon and having a buried interconnect structure for interconnection of desired ones of the semiconductor devices according to a predetermined interconnection pattern and a method of making the same is disclosed. The wafer structure comprises a primary substrate having a first thickness appropriate for the formation of the desired semiconductor devices. The primary substrate further comprises a) conductive interconnection pads of a second thickness formed on a bottom surface of the primary substrate according to the predetermined interconnection pattern, b) first isolation pads of a third thickness formed on the bottom surface of the primary substrate between the conductive interconnection pads, and c) interconnection pad caps of a fourth thickness formed upon the surface of the interconnection pads opposite from the primary substrate, wherein the interconnection pad caps comprise a material suitable for wafer bonding, and further wherein the total thickness of the second thickness and the fourth thickness equals the third thickness. The structure further comprises a secondary substrate having an oxide layer thereon bonded to the interconnection pad caps and the first isolation pads of the primary wafer.

    摘要翻译： 公开了一种适于在其上形成半导体器件的晶片结构，并且具有用于根据预定互连图案互连所需半导体器件的掩埋互连结构及其制造方法。 晶片结构包括具有适于形成期望的半导体器件的第一厚度的初级衬底。 主衬底还包括：a）根据预定互连图案形成在初级衬底的底表面上的第二厚度的导电互连衬垫，b）形成在第一衬底的底表面上的第三厚度的第一隔离衬垫 导电互连焊盘，以及c）形成在与主基板相对的互连焊盘的表面上的第四厚度的互连焊盘盖，其中互连焊盘帽包括适于晶片接合的材料，并且其中第二厚度 厚度和第四厚度等于第三厚度。 该结构还包括其上结合有互连衬垫帽和主晶片的第一隔离垫的氧化物层的二次衬底。