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    Methods of Forming Integrated Circuit Devices Having Anisotropically-Oxidized Nitride Layers
    1.
    发明申请
    Methods of Forming Integrated Circuit Devices Having Anisotropically-Oxidized Nitride Layers 失效
    形成具有各向异性氧化氮化物层的集成电路器件的方法

    公开(公告)号：US20100029073A1

    公开(公告)日：2010-02-04

    申请号：US12468296

    申请日：2009-05-19

    申请人： Jae-Hwa Park ,  Jong-Min Baek ,  Gil-Heyun Choi ,  Hee-Sook Park

    发明人： Jae-Hwa Park ,  Jong-Min Baek ,  Gil-Heyun Choi ,  Hee-Sook Park

    IPC分类号： H01L21/336 ,  H01L21/3105

    CPC分类号： H01L29/4941 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/3105 ,  H01L29/6653

    摘要： Methods of forming integrated circuit devices include forming a gate electrode on a substrate and forming a nitride layer on a sidewall and upper surface of the gate electrode. The nitride layer is then anisotropically oxidized under conditions that cause a first portion of the nitride layer extending on the upper surface of the gate electrode to be more heavily oxidized relative to a second portion of the nitride layer extending on the sidewall of the gate electrode. A ratio of a thickness of an oxidized first portion of the nitride layer relative to a thickness of an oxidized second portion of the nitride layer may be in a range from about 3:1 to about 7:1.

    摘要翻译： 形成集成电路器件的方法包括在衬底上形成栅电极，并在栅电极的侧壁和上表面上形成氮化物层。 然后在使得在栅电极的上表面上延伸的氮化物层的第一部分相对于在栅电极的侧壁上延伸的氮化物层的第二部分被更大程度地氧化的条件下，各向异性地氧化氮化物层。 氮化物层的氧化的第一部分的厚度相对于氮化物层的氧化的第二部分的厚度的比例可以在约3:1至约7:1的范围内。

    Methods of Forming Integrated Circuit Devices Having Anisotropically-Oxidized Nitride Layers
    3.
    发明申请
    Methods of Forming Integrated Circuit Devices Having Anisotropically-Oxidized Nitride Layers 审中-公开
    形成具有各向异性氧化氮化物层的集成电路器件的方法

    公开(公告)号：US20120100708A1

    公开(公告)日：2012-04-26

    申请号：US13176314

    申请日：2011-07-05

    申请人： Jae-Hwa Park ,  Jong-Min Baek ,  Gil-Heyun Choi ,  Hee-Sook Park

    发明人： Jae-Hwa Park ,  Jong-Min Baek ,  Gil-Heyun Choi ,  Hee-Sook Park

    IPC分类号： H01L21/28

    CPC分类号： H01L29/4941 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/3105 ,  H01L29/6653

    摘要： Methods of forming integrated circuit devices include forming a gate electrode on a substrate and forming a nitride layer on a sidewall and upper surface of the gate electrode. The nitride layer is then anisotropically oxidized under conditions that cause a first portion of the nitride layer extending on the upper surface of the gate electrode to be more heavily oxidized relative to a second portion of the nitride layer extending on the sidewall of the gate electrode. A ratio of a thickness of an oxidized first portion of the nitride layer relative to a thickness of an oxidized second portion of the nitride layer may be in a range from about 3:1 to about 7:1.

    摘要翻译： 形成集成电路器件的方法包括在衬底上形成栅电极，并在栅电极的侧壁和上表面上形成氮化物层。 然后在使得在栅电极的上表面上延伸的氮化物层的第一部分相对于在栅电极的侧壁上延伸的氮化物层的第二部分被更大程度地氧化的条件下，各向异性地氧化氮化物层。 氮化物层的氧化的第一部分的厚度相对于氮化物层的氧化的第二部分的厚度的比例可以在约3:1至约7:1的范围内。

    Methods of forming integrated circuit devices having anisotropically-oxidized nitride layers
    6.
    发明授权
    Methods of forming integrated circuit devices having anisotropically-oxidized nitride layers 失效
    形成具有各向异性氧化的氮化物层的集成电路器件的方法

    公开(公告)号：US07989333B2

    公开(公告)日：2011-08-02

    申请号：US12468296

    申请日：2009-05-19

    申请人： Jae-Hwa Park ,  Jong-Min Baek ,  Gil-Heyun Choi ,  Hee-Sook Park

    发明人： Jae-Hwa Park ,  Jong-Min Baek ,  Gil-Heyun Choi ,  Hee-Sook Park

    IPC分类号： H01L21/3205

    CPC分类号： H01L29/4941 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/3105 ,  H01L29/6653

    摘要： Methods of forming integrated circuit devices include forming a gate electrode on a substrate and forming a nitride layer on a sidewall and upper surface of the gate electrode. The nitride layer is then anisotropically oxidized under conditions that cause a first portion of the nitride layer extending on the upper surface of the gate electrode to be more heavily oxidized relative to a second portion of the nitride layer extending on the sidewall of the gate electrode. A ratio of a thickness of an oxidized first portion of the nitride layer relative to a thickness of an oxidized second portion of the nitride layer may be in a range from about 3:1 to about 7:1.

    摘要翻译： 形成集成电路器件的方法包括在衬底上形成栅电极，并在栅电极的侧壁和上表面上形成氮化物层。 然后在使得在栅电极的上表面上延伸的氮化物层的第一部分相对于在栅电极的侧壁上延伸的氮化物层的第二部分被更大程度地氧化的条件下，各向异性地氧化氮化物层。 氮化物层的氧化的第一部分的厚度相对于氮化物层的氧化的第二部分的厚度的比例可以在约3:1至约7:1的范围内。

    Methods of manufacturing Semiconductor Devices Including PMOS and NMOS Transistors Having Different Gate Structures
    7.
    发明申请
    Methods of manufacturing Semiconductor Devices Including PMOS and NMOS Transistors Having Different Gate Structures 审中-公开
    包括具有不同栅极结构的PMOS和NMOS晶体管的半导体器件的制造方法

    公开(公告)号：US20100120211A1

    公开(公告)日：2010-05-13

    申请号：US12613746

    申请日：2009-11-06

    申请人： Jae-Hwa Park ,  Gil-Heyun Choi ,  Hee-Sook Park ,  Jong-Min Baek

    发明人： Jae-Hwa Park ,  Gil-Heyun Choi ,  Hee-Sook Park ,  Jong-Min Baek

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823857 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/105 ,  H01L27/1052

    摘要： A semiconductor device may include a semiconductor substrate having first and second regions. A first gate structure on the first region of the semiconductor substrate may include a metal oxide dielectric layer on the first region of the semiconductor substrate and a first conductive layer on the metal oxide dielectric layer. First and second source/drain regions of a first conductivity type may be provided in the first region of the semiconductor substrate on opposite sides of the first gate structure. A second gate structure on the second region of the semiconductor substrate may include a silicon oxide based dielectric layer and a second conductive layer on the silicon oxide based dielectric layer. First and second source/drain regions of a second conductivity type may be provided in the second region of the semiconductor substrate on opposite sides of the second gate structure, wherein the first and second conductivity types are different. Related methods are also discussed.

    摘要翻译： 半导体器件可以包括具有第一和第二区域的半导体衬底。 半导体衬底的第一区域上的第一栅极结构可以包括在半导体衬底的第一区域上的金属氧化物电介质层和金属氧化物电介质层上的第一导电层。 可以在第一栅极结构的相对侧的半导体衬底的第一区域中设置第一导电类型的第一和第二源极/漏极区域。 半导体衬底的第二区域上的第二栅极结构可以包括基于氧化硅的电介质层和在氧化硅基介电层上的第二导电层。 可以在第二栅极结构的相对侧的半导体衬底的第二区域中提供第二导电类型的第一和第二源极/漏极区域，其中第一和第二导电类型不同。 还讨论了相关方法。