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    VARACTORLESS TUNABLE OSCILLATOR
    1.
    发明申请
    VARACTORLESS TUNABLE OSCILLATOR 有权
    无级可调谐振荡器

    公开(公告)号：US20120212300A1

    公开(公告)日：2012-08-23

    申请号：US13030843

    申请日：2011-02-18

    申请人： Yiwu Tang ,  Jaehyouk Choi ,  Jong Min Park ,  Narathong Chiewcharn

    发明人： Yiwu Tang ,  Jaehyouk Choi ,  Jong Min Park ,  Narathong Chiewcharn

    IPC分类号： H03B5/12

    CPC分类号： H03B5/1228 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1243 ,  H03B5/1256 ,  H03B5/1296

    摘要： A tunable oscillator circuit is disclosed. The tunable oscillator circuit includes an inductor/capacitor (LC) tank circuit comprising a primary inductor coupled in parallel with a first capacitor bank. The LC tank resonates to produce an oscillating voltage at a frequency. The tunable oscillator circuit also includes a 90 degree phase shift buffer coupled to the LC tank and a transconductor. The transconductor is coupled to the 90 degree phase shift buffer and a secondary inductor. The tunable oscillator circuit also includes a secondary inductor that is inductively coupled to the primary inductor and receives a gain-scaled oscillating current from the transconductor. By changing the transconductance, the gain-scaled oscillating current in the secondary inductor will change, thus the effective primary inductance and the oscillation frequency can be tuned.

    摘要翻译： 公开了一种可调振荡器电路。 可调振荡器电路包括电感器/电容器（LC）槽电路，其包括与第一电容器组并联耦合的初级电感器。 LC谐振腔产生振荡电压频率。 可调振荡器电路还包括耦合到LC箱和跨导体的90度相移缓冲器。 跨导体耦合到90度相移缓冲器和次级电感器。 可调谐振荡器电路还包括次级电感器，该次级电感器感应耦合到初级电感器并且从跨导体接收增益定标的振荡电流。 通过改变跨导，次级电感器中的增益调节振荡电流将发生变化，从而可以调节有效初级电感和振荡频率。

    CONFIGURABLE MULTI-MODE OSCILLATORS
    2.
    发明申请
    CONFIGURABLE MULTI-MODE OSCILLATORS 审中-公开
    可配置的多模振荡器

    公开(公告)号：US20140009236A1

    公开(公告)日：2014-01-09

    申请号：US13541258

    申请日：2012-07-03

    申请人： Jaehyouk Choi ,  Yiwu Tang

    发明人： Jaehyouk Choi ,  Yiwu Tang

    IPC分类号： H03B5/12

    CPC分类号： H03B5/1215 ,  H03B5/1225 ,  H03B5/1228 ,  H03B5/1234 ,  H03B5/124 ,  H03B5/1278 ,  H03B2200/0046 ,  H03B2200/0048 ,  H03B2200/0062 ,  H03B2200/0082

    摘要： Multi-mode oscillators supporting multiple modes and having different desirable characteristics (e.g., good phase noise or low power consumption) in different modes are disclosed. In an exemplary design, an apparatus includes first and second transistors of a first transistor type (e.g., NMOS transistors) and third and fourth transistors of a second transistor type (e.g., PMOS transistors) for a multi-mode oscillator. The third and fourth transistors are coupled (e.g., directly) to the first and second transistors. The first and second transistors are enabled in a first mode to provide signal gain for the oscillator and generate an oscillator signal in the first mode. The first to fourth transistors are enabled in a second mode to provide signal gain for the oscillator and generate the oscillator signal in the second mode. Different supply voltages may be provided at different supply nodes of the oscillator in the first and second modes.

    摘要翻译： 公开了支持多种模式并具有不同模式的不同期望特性（例如良好的相位噪声或低功耗）的多模式振荡器。 在示例性设计中，装置包括第一晶体管类型（例如，NMOS晶体管）的第一和第二晶体管以及用于多模式振荡器的第二晶体管类型（例如PMOS晶体管）的第三和第四晶体管。 第三和第四晶体管耦合（例如，直接）到第一和第二晶体管。 第一和第二晶体管在第一模式中被使能以提供振荡器的信号增益并且在第一模式中产生振荡器信号。 第一至第四晶体管在第二模式下被使能以提供振荡器的信号增益并在第二模式中产生振荡器信号。 可以在第一和第二模式中在振荡器的不同供应节点处提供不同的电源电压。

    Varactorless tunable oscillator
    3.
    发明授权
    Varactorless tunable oscillator 有权
    无变矩器可调谐振荡器

    公开(公告)号：US08665033B2

    公开(公告)日：2014-03-04

    申请号：US13030843

    申请日：2011-02-18

    申请人： Yiwu Tang ,  Jaehyouk Choi ,  Jongmin Park ,  Chiewcharn Narathong

    发明人： Yiwu Tang ,  Jaehyouk Choi ,  Jongmin Park ,  Chiewcharn Narathong

    IPC分类号： H03B5/08 ,  H03B5/18

    CPC分类号： H03B5/1228 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1243 ,  H03B5/1256 ,  H03B5/1296

    摘要： A tunable oscillator circuit is disclosed. The tunable oscillator circuit includes an inductor/capacitor (LC) tank circuit comprising a primary inductor coupled in parallel with a first capacitor bank. The LC tank resonates to produce an oscillating voltage at a frequency. The tunable oscillator circuit also includes a 90 degree phase shift buffer coupled to the LC tank and a transconductor. The transconductor is coupled to the 90 degree phase shift buffer and a secondary inductor. The tunable oscillator circuit also includes a secondary inductor that is inductively coupled to the primary inductor and receives a gain-scaled oscillating current from the transconductor. By changing the transconductance, the gain-scaled oscillating current in the secondary inductor will change, thus the effective primary inductance and the oscillation frequency can be tuned.

    摘要翻译： 公开了一种可调振荡器电路。 可调振荡器电路包括电感器/电容器（LC）槽电路，其包括与第一电容器组并联耦合的初级电感器。 LC谐振腔产生振荡电压频率。 可调振荡器电路还包括耦合到LC箱和跨导体的90度相移缓冲器。 跨导体耦合到90度相移缓冲器和次级电感器。 可调谐振荡器电路还包括次级电感器，该次级电感器感应耦合到初级电感器并且从跨导体接收增益定标的振荡电流。 通过改变跨导，次级电感器中的增益调节振荡电流将发生变化，从而可以调节有效初级电感和振荡频率。

    Buffer input impedance compensation in a reference clock signal buffer
    4.
    发明授权
    Buffer input impedance compensation in a reference clock signal buffer 有权
    参考时钟信号缓冲器中的缓冲器输入阻抗补偿

    公开(公告)号：US08797110B2

    公开(公告)日：2014-08-05

    申请号：US13558660

    申请日：2012-07-26

    申请人： Bin Fan ,  Yiwu Tang ,  Kevin Hsi Huai Wang

    发明人： Bin Fan ,  Yiwu Tang ,  Kevin Hsi Huai Wang

    IPC分类号： H03B5/32

    CPC分类号： H03L3/00 ,  H04W52/029 ,  Y02D70/00 ,  Y02D70/122 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/146 ,  Y02D70/164

    摘要： A system for managing a reference clock signal includes an XO; a signal buffer coupled to the XO and configured to drive a reference clock signal generated by the XO; and a first IC coupled to the signal buffer. The first IC includes an XO input buffer configured to receive the reference clock signal, to switch between an enabled, operational state and a disabled state, and to have a first operational impedance while in the enabled state; an impedance equivalence circuit configured to be in an enabled, operational state when the XO input buffer is in its disabled state and vice versa and to have a second operational impedance while in the enabled state that is equivalent to the first operational impedance; and a control mechanism configured to switch the XO input buffer and the impedance equivalence circuit between the enabled state and the disabled state.

    摘要翻译： 用于管理参考时钟信号的系统包括XO; 耦合到XO并被配置为驱动由XO产生的参考时钟信号的信号缓冲器; 以及耦合到信号缓冲器的第一IC。 第一IC包括被配置为接收参考时钟信号的XO输入缓冲器，以在启用状态，操作状态和禁用状态之间切换，并且在处于使能状态时具有第一操作阻抗; 阻抗等效电路被配置为当XO输入缓冲器处于其禁止状态并且反之亦然时处于使能的操作状态，并且在处于等效于第一操作阻抗的使能状态下具有第二操作阻抗; 以及控制机构，被配置为在所述使能状态和所述禁用状态之间切换所述XO输入缓冲器和所述阻抗等效电路。

    Methods and apparatus for implementing phase rotation at baseband frequency for transmit diversity
    5.
    发明授权
    Methods and apparatus for implementing phase rotation at baseband frequency for transmit diversity 有权
    用于实现基带频率的相位旋转用于发射分集的方法和装置

    公开(公告)号：US08160513B2

    公开(公告)日：2012-04-17

    申请号：US12185041

    申请日：2008-08-01

    申请人： Yiwu Tang ,  Mahim Ranjan ,  Marco Cassia ,  Christian Holenstein

    发明人： Yiwu Tang ,  Mahim Ranjan ,  Marco Cassia ,  Christian Holenstein

    IPC分类号： H04B7/02 ,  H04B1/02

    CPC分类号： H04B7/0682 ,  H04L1/0618 ,  H04L1/08

    摘要： An apparatus for implementing phase rotation at baseband frequency for transmit diversity may include a primary transmit signal path and a diversity transmit signal path. Both the primary transmit signal path and the diversity transmit signal path may receive a primary transmit signal. A signal selector within the diversity transmit signal path may perform phase rotation with respect to the primary transmit signal while the primary transmit signal is at a baseband frequency, thereby producing a diversity transmit signal.

    摘要翻译： 用于实现用于发射分集的基带频率的相位旋转的装置可以包括主发射信号路径和分集发射信号路径。 主发射信号路径和分集发射信号路径都可以接收主发射信号。 在主发射信号处于基带频率的同时，分集发射信号路径内的信号选择器可以相对于主发射信号执行相位旋转，从而产生分集发射信号。

    Programmable varactor for VCO gain compensation and phase noise reduction
    8.
    发明授权
    Programmable varactor for VCO gain compensation and phase noise reduction 有权
    用于VCO增益补偿和相位降噪的可编程变容二极管

    公开(公告)号：US07612626B2

    公开(公告)日：2009-11-03

    申请号：US11835499

    申请日：2007-08-08

    申请人： Yiwu Tang

    发明人： Yiwu Tang

    IPC分类号： H03B5/12

    CPC分类号： H03L7/099 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1265 ,  H03B5/1278 ,  H03B2200/005

    摘要： A programmable varactor apparatus may include multiple binary weighted varactors controlled by multiple digital varactor bits. A programmable varactor apparatus may include a plurality of binary weighted varactors, and a control to selectively disable one or more of the plurality of binary weighted varactors to decrease an effective capacitance of the programmable varactor apparatus. A method for changing an effective capacitance of a programmable varactor apparatus may include providing a plurality of binary weighted varactors, and disabling one or more of the plurality of binary weighted varactors to decrease the effective capacitance of the programmable varactor apparatus.

    摘要翻译： 可编程变容二极管装置可以包括由多个数字变容二极管控制的多个二进制加权变容二极管。 可编程可变电抗器装置可以包括多个二进制加权变容二极管，以及用于选择性地禁用多个二进制加权变容二极管中的一个或多个以减小可编程变容二极管装置的有效电容的控制。 用于改变可编程变容二极管装置的有效电容的方法可以包括提供多个二进制加权变容二极管，以及禁用多个二进制加权变容二极管中的一个或多个，以减小可编程变容二极管装置的有效电容。

    BUFFER INPUT IMPEDANCE COMPENSATION IN A REFERENCE CLOCK SIGNAL BUFFER
    9.
    发明申请
    BUFFER INPUT IMPEDANCE COMPENSATION IN A REFERENCE CLOCK SIGNAL BUFFER 有权
    参考时钟信号缓冲器中的缓冲器输入阻抗补偿

    公开(公告)号：US20140028411A1

    公开(公告)日：2014-01-30

    申请号：US13558660

    申请日：2012-07-26

    申请人： Bin Fan ,  Yiwu Tang ,  Kevin Hsi Huai Wang

    发明人： Bin Fan ,  Yiwu Tang ,  Kevin Hsi Huai Wang

    IPC分类号： H03L3/00

    CPC分类号： H03L3/00 ,  H04W52/029 ,  Y02D70/00 ,  Y02D70/122 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/146 ,  Y02D70/164

    摘要： A system for managing a reference clock signal includes an XO; a signal buffer coupled to the XO and configured to drive a reference clock signal generated by the XO; and a first IC coupled to the signal buffer. The first IC includes an XO input buffer configured to receive the reference clock signal, to switch between an enabled, operational state and a disabled state, and to have a first operational impedance while in the enabled state; an impedance equivalence circuit configured to be in an enabled, operational state when the XO input buffer is in its disabled state and vice versa and to have a second operational impedance while in the enabled state that is equivalent to the first operational impedance; and a control mechanism configured to switch the XO input buffer and the impedance equivalence circuit between the enabled state and the disabled state.

    摘要翻译： 用于管理参考时钟信号的系统包括XO; 耦合到XO并被配置为驱动由XO产生的参考时钟信号的信号缓冲器; 以及耦合到信号缓冲器的第一IC。 第一IC包括被配置为接收参考时钟信号的XO输入缓冲器，以在启用状态，操作状态和禁用状态之间切换，并且在处于使能状态时具有第一操作阻抗; 阻抗等效电路被配置为当XO输入缓冲器处于其禁止状态并且反之亦然时处于使能的操作状态，并且在处于等效于第一操作阻抗的使能状态下具有第二操作阻抗; 以及控制机构，被配置为在所述使能状态和所述禁用状态之间切换所述XO输入缓冲器和所述阻抗等效电路。