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1.发明申请公开(公告)号：US20070220239A1
公开(公告)日：2007-09-20
申请号：US11378712
申请日：2006-03-17
IPC分类号： G06F15/00
CPC分类号： G06F9/3848
摘要： In response to a property of a conditional branch instruction associated with a loop, such as a property indicating that the branch is a loop-ending branch, a count of the number of iterations of the loop is maintained, and a multi-bit value indicative of the loop iteration count is stored in a Branch History Register (BHR). In one embodiment, the multi-bit value may comprise the actual loop count, in which case the number of bits is variable. In another embodiment, the number of bits is fixed (e.g., two) and loop iteration counts are mapped to one of a fixed number of multi-bit values (e.g., four) by comparison to thresholds. Separate iteration counts may be maintained for nested loops, and a multi-bit value stored in the BHR may indicate a loop iteration count of only an inner loop, only the outer loop, or both.
摘要翻译： 响应于与循环相关联的条件转移指令的属性，例如指示分支是循环结束分支的属性，维持循环的迭代次数的计数，并且指示多位值 循环迭代计数存储在分支历史记录寄存器（BHR）中。 在一个实施例中，多比特值可以包括实际循环计数，在这种情况下，比特数是可变的。 在另一个实施例中，比特数是固定的（例如，两个），并且与阈值相比较，循环迭代计数被映射到固定数量的多比特值（例如，四）中的一个。 对于嵌套循环可以保持单独的迭代计数，并且存储在BHR中的多位值可能仅表示内部循环，仅外部循环或两者的循环迭代计数。
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公开(公告)号：US20060218354A1
公开(公告)日：2006-09-28
申请号：US11088383
申请日：2005-03-23
CPC分类号： G06F12/0804 , G06F2212/1028 , Y02D10/13
摘要： A processor includes a cache memory having at least one entry managed according to a copy-back algorithm. A global modified indicator (GMI) indicates whether any copy-back entry in the cache contains modified data. On a cache miss, if the GMI indicates that no copy-back entry in the cache contains modified data, data fetched from memory are written to the selected entry without first reading the entry. In a banked cache, two or more bank-GMIs may be associated with two or more banks. In an n-way set associative cache, n set-GMIs may be associated with the n sets. Suppressing the read to determine if the copy-back cache entry contains modified data improves processor performance and reduces power consumption.
摘要翻译： 处理器包括具有根据回写算法管理的至少一个条目的高速缓冲存储器。 全局修改指示符（GMI）指示高速缓存中是否有任何复制条目包含修改的数据。 在缓存未命中时，如果GMI指示高速缓存中没有复制条目包含已修改的数据，则从内存中读取的数据将被写入所选条目，而无需先读入条目。 在一个银行缓存中，两个或多个银行GMI可以与两个或更多个银行相关联。 在n路集合关联高速缓存中，n个集合GMI可以与n个集合相关联。 禁止读取以确定复制缓存条目是否包含修改的数据是否能够提高处理器性能并降低功耗。
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3.发明申请Systems and arrangements for promoting a line from shared to exclusive in a cache 失效在缓存中促进从共享到独占的行的系统和安排公开(公告)号：US20060212659A1
公开(公告)日：2006-09-21
申请号：US11083615
申请日：2005-03-18
CPC分类号： G06F12/0833
摘要： Systems and arrangements promoting a line from shared to exclusive in cache are contemplated. Embodiments include a cache controller adapted to determine whether a memory line for which the processor is to issue an address-only kill request resides in a fill buffer for the cache line in a shared state. If so, the cache controller may mark the fill buffer as not having completed bus transactions and issue the address-only kill request for that fill buffer. The address-only kill request may transmit to other processors on the bus and the other processors may respond by invalidating the cache entries for the memory line. Upon confirmation from the other processors, a bus arbiter may confirm the kill request, promoting the memory line already in that fill buffer to exclusive state. Once promoted, the fill buffer may be marked as having completed the bus transactions and may be written into the cache.
摘要翻译： 考虑了在缓存中促进从共享到独占的系统和布置。 实施例包括高速缓存控制器，其适于确定处理器将要发出仅地址杀死请求的存储器线是否驻留在共享状态下的高速缓存行的填充缓冲器中。 如果是这样，高速缓存控制器可以将填充缓冲区标记为没有完成总线事务并且发出针对该填充缓冲区的仅地址杀死请求。 只有地址的中断请求可以发送到总线上的其他处理器，而其他处理器可以通过使存储器线的高速缓存条目无效来进行响应。 在其他处理器确认之后，总线仲裁器可以确认杀死请求，将已经在该填充缓冲器中的存储器线路推送到独占状态。 一旦被提升，填充缓冲器可以被标记为完成总线事务并且可以被写入高速缓存。
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4.发明申请Power saving methods and apparatus to selectively enable cache bits based on known processor state 有权省电方法和装置，用于基于已知的处理器状态选择性地启用高速缓存位公开(公告)号：US20060200686A1
公开(公告)日：2006-09-07
申请号：US11073284
申请日：2005-03-04
IPC分类号： G06F1/26
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3816 , G06F12/0875 , Y02D10/13
摘要： A processor capable of fetching and executing variable length instructions is described having instructions of at least two lengths. The processor operates in multiple modes. One of the modes restricts instructions that can be fetched and executed to the longer length instructions. An instruction cache is used for storing variable length instructions and their associated predecode bit fields in an instruction cache line and storing the instruction address and processor operating mode state information at the time of the fetch in a tag line. The processor operating mode state information indicates the program specified mode of operation of the processor. The processor fetches instructions from the instruction cache for execution. As a result of an instruction fetch operation, the instruction cache may selectively enable the writing of predecode bit fields in the instruction cache and may selectively enable the reading of predecode bit fields stored in the instruction cache based on the processor state at the time of the fetch.
摘要翻译： 描述具有至少两个长度的指令的能够获取和执行可变长度指令的处理器。 处理器以多种模式运行。 其中一种模式限制了可以获取并执行到较长长度指令的指令。 指令高速缓存用于在指令高速缓存行中存储可变长度指令及其相关联的预解码位字段，并且在获取标签行时存储指令地址和处理器操作模式状态信息。 处理器操作模式状态信息指示处理器的程序指定的操作模式。 处理器从指令缓存器中获取指令以执行。 作为指令提取操作的结果，指令高速缓存可以选择性地启用指令高速缓存中的预解码位字段的写入，并且可以基于处理器状态来选择性地启用存储在指令高速缓存中的预解码位字段的读取 取。
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公开(公告)号：US20060168390A1
公开(公告)日：2006-07-27
申请号：US11040600
申请日：2005-01-21
CPC分类号： G06F12/0802 , G06F12/0851 , G06F2212/601 , Y02D10/13
摘要： Techniques for controllably allocating a portion of a plurality of memory banks as cache memory are disclosed. To this end, a configuration tracker and a bank selector are employed. The configuration tracker configures whether each memory bank is to operate in a cache or not. The bank selector has a plurality of bank distributing functions. Upon receiving an incoming address, the bank selector determines the configuration of memory banks currently operating as the cache and applies an appropriate bank distributing function based on the configuration of memory banks. The applied bank distributing function utilizes bits in the incoming address to access one of the banks configured as being in the cache.
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6.发明申请Apparatus and method for reformatting instructions before reaching a dispatch point in a superscalar processor 审中-公开在超标量处理器到达调度点之前重新格式化指令的装置和方法公开(公告)号：US20060155961A1
公开(公告)日：2006-07-13
申请号：US11030339
申请日：2005-01-06
IPC分类号： G06F9/30
CPC分类号： G06F9/3802 , G06F9/382
摘要： Method and apparatus for reformatting instructions in a pipelined processor. An instruction register holds a plurality of instructions received from a cache memory external to the processor. A predecoder predecodes each of the instructions and determines from an instruction operation field where the instruction fields should be placed. A multiplexer reformats architecturally aligned instructions into hardware implementation aligned instructions prior to storing into L1 cache, so that the instructions are ready for dispatch to the pipeline execution units.
摘要翻译： 用于在流水线处理器中重新格式化指令的方法和装置。 指令寄存器保存从处理器外部的高速缓冲存储器接收的多个指令。 预解码器对每个指令进行预解码，并从指令操作字段中确定应放置指令字段。 多路复用器将结构化对齐的指令重新格式化为在存储到L1高速缓存之前的硬件实现对准的指令，使得指令准备好发送到流水线执行单元。
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7.发明申请Method and apparatus for avoiding data dependency hazards in a microprocessor pipeline architecture 失效在微处理器流水线架构中避免数据依赖危害的方法和装置公开(公告)号：US20060037023A1
公开(公告)日：2006-02-16
申请号：US10916188
申请日：2004-08-11
IPC分类号： G06F9/46
CPC分类号： G06F9/3836 , G06F9/3824 , G06F9/3826 , G06F9/3838 , G06F9/3855
摘要： A method and system for avoiding various hazards for instructions which are propagating through a microprocessor pipeline. When a plurality of instructions exist within the pipeline which read and write the same value, a vector is established to distinguish the older from the newer instructions. Further, before instructions are dispatched for execution, pointers are generated which identify the particular instruction which had the operand or parameter value needed. Accordingly, by monitoring both the recent vector and pointers, dated dependency hazards can be avoided.
摘要翻译： 一种用于避免通过微处理器管道传播的指令的各种危险的方法和系统。 当流水线内存在多个读取和写入相同值的指令时，建立一个向量来区分较旧的指令。 此外，在分派指令执行之前，生成指针，该指针标识具有所需操作数或参数值的特定指令。 因此，通过监视最近的向量和指针，可以避免日期依赖危害。
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公开(公告)号：US20070174584A1
公开(公告)日：2007-07-26
申请号：US11336264
申请日：2006-01-20
IPC分类号： G06F12/00
CPC分类号： G06F9/3861 , G06F12/1027
摘要： A processor having a multistage pipeline includes a TLB and a TLB controller. In response to a TLB miss signal, the TLB controller initiates a TLB reload, requesting address translation information from either a memory or a higher-level TLB, and placing that information into the TLB. The processor flushes the instruction having the missing virtual address, and refetches the instruction, resulting in re-insertion of the instruction at an initial stage of the pipeline above the TLB access point. The initiation of the TLB reload, and the flush/refetch of the instruction, are performed substantially in parallel, and without immediately stalling the pipeline. The refetched instruction is held at a point in the pipeline above the TLB access point until the TLB reload is complete, so that the refetched instruction generates a “hit” in the TLB upon its next access.
摘要翻译： 具有多级流水线的处理器包括TLB和TLB控制器。 响应于TLB未命中信号，TLB控制器启动TLB重新加载，从存储器或更高级TLB请求地址转换信息，并将该信息放入TLB。 处理器刷新具有缺失的虚拟地址的指令，并且重新指示该指令，从而导致在TLB接入点上方的管线的初始阶段重新插入该指令。 TLB重新启动的启动以及指令的刷新/刷新基本上并行执行，并且不会立即停止管道。 重写指令在TLB接入点上方的管道中保持一段时间，直到TLB重新加载完成，这样，重写指令在下一次访问时就会在TLB中产生一个“命中”。
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9.发明申请公开(公告)号：US20070094476A1
公开(公告)日：2007-04-26
申请号：US11254898
申请日：2005-10-20
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F2212/681 , G06F2212/684
摘要： An apparatus includes a memory configured to store data, a lower level TLB, an upper level TLB, and a TLB controller. The lower level TLB and the upper level TLB are configured to store a plurality of entries, each of the entries containing an address translation information that allows a virtual address to be translated into a corresponding physical address. The TLB controller retrieves from a page table in the memory an address translation information for a desired virtual address, if the desired virtual address generates a TLB miss from the lower level TLB and from the upper level TLB, Using a single TLB write instruction, the TLB controller updates both the lower level TLB and the upper level TLB by writing the address translation information, retrieved from the page table, into the lower level TLB as well as into the upper level TLB.
摘要翻译： 一种装置包括被配置为存储数据的存储器，较低级TLB，上级TLB和TLB控制器。 下级TLB和上级TLB被配置为存储多个条目，每个条目包含允许将虚拟地址转换成对应的物理地址的地址转换信息。 如果所需的虚拟地址从较低级别的TLB和上级TLB生成TLB未命中，则TLB控制器从存储器中的页表中检索所需虚拟地址的地址转换信息。使用单个TLB写指令， TLB控制器通过将从页表中检索的地址转换信息写入下级TLB以及上级TLB来更新下级TLB和上级TLB。
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公开(公告)号：US20060294346A1
公开(公告)日：2006-12-28
申请号：US11165268
申请日：2005-06-22
IPC分类号： G06F15/00
CPC分类号： G06F9/3842 , G06F9/30054 , G06F9/3806 , G06F9/3861
摘要： In one or more embodiments, a processor includes a link return stack circuit used for storing branch return addresses, wherein a link return stack controller is configured to determine that one or more entries in the link return stack are invalid as being dependent on a mispredicted branch, and to reset the link return stack to a valid remaining entry, if any. In this manner, branch mispredictions cause dependent entries in the link return stack to be flushed from the link return stack, or otherwise invalidated, while preserving the remaining valid entries, if any, in the link return stack. In at least one embodiment, a branch information queue used for tracking predicted branches is configured to store a marker indicating whether a predicted branch has an associated entry in the link return stack, and it may store an index value identifying the specific, corresponding entry in the link return stack.
摘要翻译： 在一个或多个实施例中，处理器包括用于存储分支返回地址的链路返回堆栈电路，其中，链路返回栈控制器被配置为确定链路返回栈中的一个或多个条目是无效的，这取决于错误预测的分支 ，并将链接返回堆栈重置为有效的剩余条目（如果有）。 以这种方式，分支错误预测会导致链接返回堆栈中的相关条目从链接返回堆栈刷新，否则无效，同时保留链接返回堆栈中的剩余有效条目（如果有的话）。 在至少一个实施例中，用于跟踪预测分支的分支信息队列被配置为存储指示预测分支是否具有链接返回栈中的相关联条目的标记，并且其可以存储标识特定相应条目的索引值 链接返回堆栈。
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