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    Passing lamp assembly
    2.
    发明申请
    Passing lamp assembly 有权
    通过灯组件

    公开(公告)号：US20060002120A1

    公开(公告)日：2006-01-05

    申请号：US10880836

    申请日：2004-06-30

    Applicant: Martin Grigg ,  James Hofmann ,  Brian Pendowski

    Inventor： Martin Grigg ,  James Hofmann ,  Brian Pendowski

    IPC: F21V33/00

    CPC classification number: B62J6/005 ,  B60Q1/0483 ,  B62J6/02

    Abstract: A lamp assembly mountable on a motorcycle having first and second fork tubes. The lamp assembly includes a bracket that is attachable to only the first fork tube. The bracket is adapted to be solely supported by the first fork tube. A first light is coupled to the bracket and a second light is coupled to the bracket.

    Abstract translation: 安装在具有第一和第二叉管的摩托车上的灯组件。 灯组件包括仅可附接到第一叉管的托架。 支架适于单独由第一叉管支撑。 第一个光耦合到支架，第二个光耦合到支架。

    Mold for forming flat panel display spacers
    4.
    发明授权
    Mold for forming flat panel display spacers 失效
    用于形成平板显示隔板的模具

    公开(公告)号：US06375149B1

    公开(公告)日：2002-04-23

    申请号：US09605559

    申请日：2000-06-27

    Applicant: Jason B. Elledge ,  James Hofmann

    Inventor： Jason B. Elledge ,  James Hofmann

    IPC: B28B702

    CPC classification number: H01J9/242 ,  C03B37/01211 ,  C03B37/028 ,  C03B37/14 ,  C03B37/15 ,  G02B6/08 ,  H01J29/864 ,  H01J2329/00 ,  H01J2329/863 ,  Y10T29/49801

    Abstract: A hexagonal mold is formed by a unitary base and a unitary cover. Each of the base and the cover form three of the six surfaces of a hexagonal mold cavity when the cover is placed on top of the base. The hexagonal mold may be used to form field emission display spacers and field emission display microchannels by placing etchable single fibers in the hexagonal mold to form hexagonal multiple fiber preforms. The preforms are then drawn to form multiple fibers that are placed in a rectangular mold to form a rectangular fiber block. The rectangular fiber block is then sliced into sheets which are then placed between a field emission display baseplate and a field emission display faceplate.

    Abstract translation: 六角形模具由单一基座和整体盖板形成。 当盖子放置在基座的顶部时，基座和盖子中的每一个形成六边形模腔的六个表面中的三个。 六角形模具可用于通过将可蚀刻单纤维放置在六边形模具中以形成六边形多纤维预制件来形成场发射显示间隔件和场发射显示微通道。 然后将预成型件拉伸以形成放置在矩形模具中以形成矩形纤维块的多根纤维。 然后将矩形纤维块切片成片，然后将其放置在场发射显示基板和场发射显示面板之间。

    Method for enhancing electrode surface area in DRAM cell capacitors
    5.
    发明申请
    Method for enhancing electrode surface area in DRAM cell capacitors 失效
    提高DRAM单元电容器电极表面积的方法

    公开(公告)号：US20070048955A1

    公开(公告)日：2007-03-01

    申请号：US11514694

    申请日：2006-08-31

    Applicant: Donald Yates ,  Garry Mercaldi ,  James Hofmann

    Inventor： Donald Yates ,  Garry Mercaldi ,  James Hofmann

    IPC: H01L21/331 ,  H01L21/8222

    CPC classification number: H01L27/1085 ,  H01L27/10852 ,  H01L28/65 ,  H01L28/82 ,  H01L28/84 ,  H01L28/91

    Abstract: Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is fabricated by forming a texturizing underlayer and then depositing a conductive material thereover. In one embodiment of a method of forming the lower electrode, the texturizing layer is formed by depositing a polymeric material comprising a hydrocarbon block and a silicon-containing block, over the insulative layer of a container, and then subsequently converting the polymeric film to relief or porous nanostructures by exposure to UV radiation and ozone, resulting in a textured porous or relief silicon oxycarbide film. A conductive material is then deposited over the texturizing layer resulting in a lower electrode have an upper roughened surface. In another embodiment of a method of forming the lower electrode, the texturizing underlayer is formed by depositing overlying first and second conductive metal layers and annealing the metal layers to form surface dislocations, preferably structured as a periodic network. A conductive metal is then deposited in gaseous phase, and agglomerates onto the surface dislocations of the texturizing layer, forming nanostructures in the form of island clusters. The capacitor is completed by depositing a dielectric layer over the formed lower electrode, and forming an upper capacitor electrode over the dielectric layer. The capacitors are particularly useful in fabricating DRAM cells.

    Abstract translation: 提供了形成半导体电路中的电容器的下电极的方法以及通过这些方法形成的电容器。 下电极通过形成纹理化的底层然后在其上沉积导电材料来制造。 在形成下电极的方法的一个实施方案中，通过在容器的绝缘层上沉积包含烃嵌段和含硅嵌段的聚合材料，然后随后将聚合物膜转化为浮雕而形成该组织化层 或通过暴露于UV辐射和臭氧的多孔纳米结构，导致织构化的多孔或缓蚀硅碳化硅膜。 然后将导电材料沉积在纹理化层上，导致下部电极具有上部粗糙表面。 在形成下电极的方法的另一实施例中，通过沉积覆盖的第一和第二导电金属层并退火金属层形成优选构造为周期性网络的表面位错来形成纹理化下层。 然后将导电金属沉积在气相中，并且聚集到构造层的表面位错上，形成岛簇形式的纳米结构。 电容器通过在形成的下电极上沉积介电层并在电介质层上形成上电容器电极来完成。 电容器在制造DRAM单元时特别有用。

    Offset test pattern apparatus and method
    6.
    发明申请
    Offset test pattern apparatus and method 失效
    偏移测试图案设备和方法

    公开(公告)号：US20060253757A1

    公开(公告)日：2006-11-09

    申请号：US11121164

    申请日：2005-05-03

    Applicant: Robert Brink ,  James Hofmann ,  Max Olsen ,  Gary Schiessler ,  Lane Smith

    Inventor： Robert Brink ,  James Hofmann ,  Max Olsen ,  Gary Schiessler ,  Lane Smith

    IPC: G06F11/00 ,  G01R31/28

    CPC classification number: H04L1/244

    Abstract: Communications equipment can be tested using a test pattern encapsulated within a frame, and offsetting the test pattern in each successive frame. In equipment having a number of data latches receiving serial input, the introduction of the offset allows each latch, over time, to be exposed to the same pattern as the other latches. That is, the latches “see” different portions of the pattern at a given time, but over time, each can be exposed to the full pattern. Otherwise, each latch would “see” its own static pattern, different from the other latches, but the same over time with respect to itself. The offset can enhance diagnostic capabilities of the test pattern.

    Abstract translation: 可以使用封装在帧内的测试图案来测试通信设备，并且在每个连续帧中抵消测试模式。 在具有接收串行输入的多个数据锁存器的设备中，引入偏移允许每个锁存器随时间暴露于与其他锁存器相同的模式。 也就是说，锁定器在给定时间“看到”图案的不同部分，但是随着时间的推移，每个可以暴露于完整图案。 否则，每个锁存器将“看到”其自己的静态模式，与其他锁存器不同，但是相对于自身而言随着时间的推移相同。 该偏移可以增强测试图案的诊断功能。

    Method for making sol gel spacers for flat panel displays
    8.
    发明申请
    Method for making sol gel spacers for flat panel displays 审中-公开
    制造平板显示器用溶胶凝胶垫片的方法

    公开(公告)号：US20050112298A1

    公开(公告)日：2005-05-26

    申请号：US10978323

    申请日：2004-11-01

    Applicant: James Hofmann ,  Brian Vaartstra ,  Brenda Kraus ,  Donald Westmoreland

    Inventor： James Hofmann ,  Brian Vaartstra ,  Brenda Kraus ,  Donald Westmoreland

    IPC: B05D5/12 ,  B29C33/38 ,  B29C59/00 ,  G02F1/1339

    CPC classification number: G03F7/0017 ,  B29C33/3857 ,  G02F1/1339 ,  G02F1/13394 ,  H01J2211/36 ,  Y10T428/1059

    Abstract: The present invention describes thick film photolithographic molds, methods of making thick film photolithographic molds, and methods of using thick film photolithographic molds to form spacers on a substrate. The thick film photolithographic molds preferably comprise an epoxy bisphenol A novolac resin. The present invention also describes sol gel spacers comprising sodium silicates and potassium silicates. The thick film photolithographic molds and sol gel spacers of the present invention can be used in flat panel displays, such as field emission displays and plasma displays.

    Abstract translation: 本发明描述了厚膜光刻模具，制备厚膜光刻模具的方法，以及使用厚膜光刻模具在衬底上形成间隔物的方法。 厚膜光刻模优选包含环氧双酚A酚醛清漆树脂。 本发明还描述了包含硅酸钠和硅酸钾的溶胶凝胶间隔物。 本发明的厚膜光刻模和溶胶凝胶间隔物可用于诸如场发射显示器和等离子体显示器的平板显示器中。

    Method for enhancing electrode surface area in DRAM cell capacitors
    9.
    发明申请
    Method for enhancing electrode surface area in DRAM cell capacitors 失效

    公开(公告)号：US20060292875A1

    公开(公告)日：2006-12-28

    申请号：US11510949

    申请日：2006-08-28

    Applicant: Donald Yates ,  Garry Mercaldi ,  James Hofmann

    Inventor： Donald Yates ,  Garry Mercaldi ,  James Hofmann

    IPC: H01L21/44

    CPC classification number: H01L27/1085 ,  H01L27/10852 ,  H01L28/65 ,  H01L28/82 ,  H01L28/84 ,  H01L28/91

    Abstract: Methods for forming the lower electrode of a capacitor in a semiconductor circuit, and the capacitors formed by such methods are provided. The lower electrode is fabricated by forming a texturizing underlayer and then depositing a conductive material thereover. In one embodiment of a method of forming the lower electrode, the texturizing layer is formed by depositing a polymeric material comprising a hydrocarbon block and a silicon-containing block, over the insulative layer of a container, and then subsequently converting the polymeric film to relief or porous nanostructures by exposure to UV radiation and ozone, resulting in a textured porous or relief silicon oxycarbide film. A conductive material is then deposited over the texturizing layer resulting in a lower electrode have an upper roughened surface. In another embodiment of a method of forming the lower electrode, the texturizing underlayer is formed by depositing overlying first and second conductive metal layers and annealing the metal layers to form surface dislocations, preferably structured as a periodic network. A conductive metal is then deposited in gaseous phase, and agglomerates onto the surface dislocations of the texturizing layer, forming nanostructures in the form of island clusters. The capacitor is completed by depositing a dielectric layer over the formed lower electrode, and forming an upper capacitor electrode over the dielectric layer. The capacitors are particularly useful in fabricating DRAM cells.

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