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公开(公告)号：US09252204B2
公开(公告)日：2016-02-02
申请号：US13233752
申请日：2011-09-15
IPC分类号： H01L49/02
CPC分类号： H01L28/90
摘要： A MIM capacitor includes a dielectric cap that enhances performance and reduces damage to MIM insulators during manufacture. A cavity is formed in an insulative substrate, such as a back end of line dielectric layer, and a first metal layer and an insulator layer are conformally deposited. A second metal layer may be deposited conformally and/or to fill a remaining portion of the cavity. The dielectric cap may be an extra layer of insulative material deposited at ends of the insulator at an opening of the cavity and may also be formed as part of the insulator layer.
摘要翻译： MIM电容器包括在制造期间增强性能并减少对MIM绝缘体的损坏的电介质盖。 在绝缘基板（例如线路介质层的后端）中形成空腔，并且第一金属层和绝缘体层被共形沉积。 可以共形地沉积第二金属层和/或填充空腔的剩余部分。 电介质盖可以是在空腔的开口处沉积在绝缘体的端部处的绝缘材料的额外层，并且还可以形成为绝缘体层的一部分。
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公开(公告)号：US20130069199A1
公开(公告)日：2013-03-21
申请号：US13233752
申请日：2011-09-15
CPC分类号： H01L28/90
摘要： A MIM capacitor includes a dielectric cap that enhances performance and reduces damage to MIM insulators during manufacture. A cavity is formed in an insulative substrate, such as a back end of line dielectric layer, and a first metal layer and an insulator layer are conformally deposited. A second metal layer may be deposited conformally and/or to fill a remaining portion of the cavity. The dielectric cap may be an extra layer of insulative material deposited at ends of the insulator at an opening of the cavity and may also be formed as part of the insulator layer.
摘要翻译： MIM电容器包括在制造期间增强性能并减少对MIM绝缘体的损坏的电介质盖。 在绝缘基板（例如线路介质层的后端）中形成空腔，并且第一金属层和绝缘体层被共形沉积。 可以共形地沉积第二金属层和/或填充空腔的剩余部分。 电介质盖可以是在空腔的开口处沉积在绝缘体的端部处的绝缘材料的额外层，并且还可以形成为绝缘体层的一部分。
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公开(公告)号：US07893468B2
公开(公告)日：2011-02-22
申请号：US12129716
申请日：2008-05-30
IPC分类号： H01L29/72
CPC分类号： H01L27/14647 , H01L27/14632 , H01L27/14641 , H01L27/14687
摘要： A complementary metal-oxide-semiconductor (CMOS) image sensor comprises a first photosensitive diode comprising a first semiconductor material is formed in a first semiconductor substrate. A second photosensitive diode comprising a second semiconductor material, which has a different light detection wavelength range than the first semiconductor material, is formed in a second semiconductor substrate. Semiconductor devices for holding and detecting charges comprising a sensing circuit of the CMOS image sensor may also be formed in the second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are bonded so that the first photosensitive diode is located underneath the second photosensitive diode. The vertical stack of the first and second photosensitive diodes detects light in the combined detection wavelength range of the first and second semiconductor materials. Sensing devices may be shared between the first and second photosensitive diodes.
摘要翻译： 互补金属氧化物半导体（CMOS）图像传感器包括在第一半导体衬底中形成包括第一半导体材料的第一感光二极管。 在第二半导体衬底中形成包括具有与第一半导体材料不同的光检测波长范围的第二半导体材料的第二光敏二极管。 用于保持和检测包括CMOS图像传感器的感测电路的电荷的半导体器件也可以形成在第二半导体衬底中。 第一半导体衬底和第二半导体衬底被接合，使得第一感光二极管位于第二感光二极管的下方。 第一和第二光敏二极管的垂直堆叠检测第一和第二半导体材料的组合检测波长范围内的光。 感测装置可以在第一和第二光敏二极管之间共享。
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公开(公告)号：US07883916B2
公开(公告)日：2011-02-08
申请号：US12129714
申请日：2008-05-30
IPC分类号： H01L21/00
CPC分类号： H01L27/14647 , H01L27/14609 , H01L27/14641 , H01L27/14683
摘要： A complementary metal-oxide-semiconductor (CMOS) image sensor comprises a first photosensitive diode comprising a first semiconductor material is formed in a first semiconductor substrate. A second photosensitive diode comprising a second semiconductor material, which has a different light detection wavelength range than the first semiconductor material, is formed in a second semiconductor substrate. Semiconductor devices for holding and detecting charges comprising a sensing circuit of the CMOS image sensor may also be formed in the second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are bonded so that the first photosensitive diode is located underneath the second photosensitive diode. The vertical stack of the first and second photosensitive diodes detects light in the combined detection wavelength range of the first and second semiconductor materials. Sensing devices may be shared between the first and second photosensitive diodes.
摘要翻译： 互补金属氧化物半导体（CMOS）图像传感器包括在第一半导体衬底中形成包括第一半导体材料的第一感光二极管。 在第二半导体衬底中形成包括具有与第一半导体材料不同的光检测波长范围的第二半导体材料的第二光敏二极管。 用于保持和检测包括CMOS图像传感器的感测电路的电荷的半导体器件也可以形成在第二半导体衬底中。 第一半导体衬底和第二半导体衬底被接合，使得第一感光二极管位于第二感光二极管的下方。 第一和第二光敏二极管的垂直堆叠检测第一和第二半导体材料的组合检测波长范围内的光。 感测装置可以在第一和第二光敏二极管之间共享。
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公开(公告)号：US07707535B2
公开(公告)日：2010-04-27
申请号：US11849461
申请日：2007-09-04
申请人： Timothy G. Dunham , Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Valarmathi C. Shanmugam
发明人： Timothy G. Dunham , Robert K. Leidy , Kevin N. Ogg , Richard J. Rassel , Valarmathi C. Shanmugam
IPC分类号： G06F17/50
CPC分类号： G03F7/70475 , G03F7/70466 , G03F7/70691
摘要： Stitched integrated circuit (IC) chip layout design structures are disclosed. In one embodiment, a design structure embodied in a machine readable medium used in a design process includes: an integrated circuit (IC) chip layout exceeding a size of a photolithography tool field, the IC chip layout including: a plurality of stitched regions including at least one redundant stitched region or at least one unique stitched region; and for each stitched region: a boundary identification identifying a boundary of the stitched region at which stitching occurs.
摘要翻译： 公开了拼接集成电路（IC）芯片布局设计结构。 在一个实施例中，在设计过程中使用的机器可读介质中体现的设计结构包括：超过光刻工具领域尺寸的集成电路（IC）芯片布局，所述IC芯片布局包括：多个缝合区域， 至少一个冗余缝合区域或至少一个独特的缝合区域; 并且针对每个缝合区域：识别发生缝合的缝合区域的边界的边界标识。
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公开(公告)号：US20090294813A1
公开(公告)日：2009-12-03
申请号：US12129716
申请日：2008-05-30
IPC分类号： H01L27/146
CPC分类号： H01L27/14647 , H01L27/14632 , H01L27/14641 , H01L27/14687
摘要： A complementary metal-oxide-semiconductor (CMOS) image sensor comprises a first photosensitive diode comprising a first semiconductor material is formed in a first semiconductor substrate. A second photosensitive diode comprising a second semiconductor material, which has a different light detection wavelength range than the first semiconductor material, is formed in a second semiconductor substrate. Semiconductor devices for holding and detecting charges comprising a sensing circuit of the CMOS image sensor may also be formed in the second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are bonded so that the first photosensitive diode is located underneath the second photosensitive diode. The vertical stack of the first and second photosensitive diodes detects light in the combined detection wavelength range of the first and second semiconductor materials. Sensing devices may be shared between the first and second photosensitive diodes.
摘要翻译： 互补金属氧化物半导体（CMOS）图像传感器包括在第一半导体衬底中形成包括第一半导体材料的第一感光二极管。 在第二半导体衬底中形成包括具有与第一半导体材料不同的光检测波长范围的第二半导体材料的第二光敏二极管。 用于保持和检测包括CMOS图像传感器的感测电路的电荷的半导体器件也可以形成在第二半导体衬底中。 第一半导体衬底和第二半导体衬底被接合，使得第一感光二极管位于第二感光二极管的下方。 第一和第二光敏二极管的垂直堆叠检测第一和第二半导体材料的组合检测波长范围内的光。 感测装置可以在第一和第二光敏二极管之间共享。
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7.发明申请STITCHED CIRCUITRY REGION BOUNDARY INDENTIFICATION FOR STITCHED IC CHIP LAYOUT 有权针对IC芯片布局布线的电路区域边界标注公开(公告)号：US20090276748A1
公开(公告)日：2009-11-05
申请号：US12112329
申请日：2008-04-30
IPC分类号： G06F17/50
CPC分类号： G03F7/70475
摘要： Stitched circuitry region boundary identification for a stitched IC chip layout is presented along with a related IC chip and design structure. One method includes obtaining a circuit design for an integrated circuit (IC) chip layout that exceeds a size of a photolithography tool field, wherein the IC chip layout includes a stitched circuitry region; and modifying the IC chip layout to include a boundary identification identifying a boundary of the stitched circuitry region at which stitching occurs, wherein the boundary identification takes the form of a negative space in the IC chip layout. One IC chip may include a plurality of stitched circuitry regions; and a boundary identification identifying a boundary between a pair of the stitched circuitry regions, wherein the boundary identification takes the form of a negative space in a layer of the IC chip.
摘要翻译： 针对IC芯片布线的缝合电路区域边界识别以及相关的IC芯片和设计结构。 一种方法包括获得超过光刻工具领域的尺寸的集成电路（IC）芯片布局的电路设计，其中IC芯片布局包括缝合电路区域; 以及修改IC芯片布局以包括标识发生缝合的缝合电路区域的边界的边界标识，其中边界识别在IC芯片布局中采取负空间的形式。 一个IC芯片可以包括多个缝合电路区域; 以及识别一对缝合电路区域之间的边界的边界识别，其中边界识别在IC芯片的层中采取负空间的形式。
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公开(公告)号：US08709855B2
公开(公告)日：2014-04-29
申请号：US12133379
申请日：2008-06-05
IPC分类号： H01L21/00
CPC分类号： H01L23/552 , H01L27/14623 , H01L27/14636 , H01L2924/0002 , H01L2924/00
摘要： A conductive light shield is formed over a first dielectric layer of a via level in a metal interconnect structure. The conductive light shield is covers a floating drain of an image sensor pixel cell. A second dielectric layer is formed over the conductive light shield and at least one via extending from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive image sensor pixel cell is less prone to noise due to the blockage of light over the floating drain by the conductive light shield.
摘要翻译： 在金属互连结构中的通孔级的第一介电层上形成导电屏蔽。 导电屏蔽覆盖图像传感器像素单元的浮动漏极。 在导电光屏蔽上形成第二电介质层，并且在金属互连结构中形成有从第二电介质层的顶表面延伸到第一介电层的底表面的至少一个通孔。 导电屏蔽可以形成在半导体衬底的顶表面和第一金属线电平之间的接触电平内，或者可以通过两个金属线电平之间的电平形成在任何金属互连中。 本发明的图像传感器像素单元由于在导电屏蔽层上的浮动漏极上的光阻塞而不容易产生噪声。
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公开(公告)号：US20110072409A1
公开(公告)日：2011-03-24
申请号：US12951674
申请日：2010-11-22
IPC分类号： G06F17/50
CPC分类号： H01L27/14647 , H01L27/14632 , H01L27/14641 , H01L27/14687
摘要： A complementary metal-oxide-semiconductor (CMOS) image sensor comprises a first photosensitive diode comprising a first semiconductor material is formed in a first semiconductor substrate. A second photosensitive diode comprising a second semiconductor material, which has a different light detection wavelength range than the first semiconductor material, is formed in a second semiconductor substrate. Semiconductor devices for holding and detecting charges comprising a sensing circuit of the CMOS image sensor may also be formed in the second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are bonded so that the first photosensitive diode is located underneath the second photosensitive diode. The vertical stack of the first and second photosensitive diodes detects light in the combined detection wavelength range of the first and second semiconductor materials. Sensing devices may be shared between the first and second photosensitive diodes.
摘要翻译： 互补金属氧化物半导体（CMOS）图像传感器包括在第一半导体衬底中形成包括第一半导体材料的第一感光二极管。 在第二半导体衬底中形成包括具有与第一半导体材料不同的光检测波长范围的第二半导体材料的第二光敏二极管。 用于保持和检测包括CMOS图像传感器的感测电路的电荷的半导体器件也可以形成在第二半导体衬底中。 第一半导体衬底和第二半导体衬底被接合，使得第一感光二极管位于第二感光二极管的下方。 第一和第二光敏二极管的垂直堆叠检测第一和第二半导体材料的组合检测波长范围内的光。 感测装置可以在第一和第二光敏二极管之间共享。
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公开(公告)号：US20090303366A1
公开(公告)日：2009-12-10
申请号：US12133380
申请日：2008-06-05
IPC分类号： H04N5/335
CPC分类号： H01L27/14623 , H01L27/14609 , H01L27/14632 , H01L27/14643
摘要： A CMOS image sensor pixel includes a conductive light shield, which is located between a first dielectric layer and a second dielectric layer. At least one via extends from a top surface of the second dielectric layer to a bottom surface of the first dielectric layer is formed in the metal interconnect structure. The conductive light shield may be formed within a contact level between a top surface of a semiconductor substrate and a first metal line level, or may be formed in any metal interconnect via level between two metal line levels. The inventive CMOS image sensor pixel enables reduction of noise in the signal stored in the floating drain.
摘要翻译： CMOS图像传感器像素包括位于第一介电层和第二介电层之间的导电屏蔽。 在金属互连结构中形成有至少一个通孔从第二电介质层的顶表面延伸到第一介电层的底表面。 导电屏蔽可以形成在半导体衬底的顶表面和第一金属线电平之间的接触电平内，或者可以通过两个金属线电平之间的电平形成在任何金属互连中。 本发明的CMOS图像传感器像素能够减少存储在浮动漏极中的信号中的噪声。
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