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    Process for producing an integrated circuit
    3.
    发明授权
    Process for producing an integrated circuit 有权
    集成电路的制造方法

    公开(公告)号：US08877622B2

    公开(公告)日：2014-11-04

    申请号：US13811792

    申请日：2011-07-22

    申请人： Thierry Poiroux ,  Sébastien Barnola ,  Yves Morand

    发明人： Thierry Poiroux ,  Sébastien Barnola ,  Yves Morand

    IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/8234 ,  H01L27/11 ,  H01L27/115 ,  H01L21/768

    CPC分类号： H01L21/823468 ,  H01L21/76897 ,  H01L21/823456 ,  H01L21/823475 ,  H01L27/11 ,  H01L27/11521

    摘要： A process for producing an integrated circuit on the surface of a substrate, the process including: producing a first layer, including active zones and insulating zones, on the surface of the substrate; producing gate zones on the surface of the first layer, the gate zones each being surrounded by insulating spacers; producing source/drain electrodes; producing a dielectric layer between the insulating spacers, the dielectric layer having an upper surface level with the upper surfaces of the gate zones; partially etching each gate zone so as to lower the upper surface of a first part of each gate zone; and depositing an insulating dielectric layer on the first parts of the gate zones.

    摘要翻译： 一种用于在基板表面上制造集成电路的方法，所述方法包括：在所述基板的表面上产生包括有源区和绝缘区的第一层; 在所述第一层的表面上产生栅极区域，所述栅极区域各自被绝缘间隔物包围; 产生源极/漏极; 在所述绝缘间隔物之间​​产生电介质层，所述电介质层具有与所述栅极区的上表面的上表面水平; 部分地蚀刻每个栅极区，以便降低每个栅极区的第一部分的上表面; 以及在栅极区域的第一部分上沉积绝缘介电层。

    Method for stabilizing germanium nanowires obtained by condensation
    5.
    发明授权
    Method for stabilizing germanium nanowires obtained by condensation 有权
    通过冷凝获得的锗纳米线的稳定化方法

    公开(公告)号：US08349667B2

    公开(公告)日：2013-01-08

    申请号：US12875729

    申请日：2010-09-03

    申请人： Emeline Saracco ,  Jean-Francois Damlencourt ,  Thierry Poiroux

    发明人： Emeline Saracco ,  Jean-Francois Damlencourt ,  Thierry Poiroux

    IPC分类号： H01L21/336

    CPC分类号： H01L29/78696 ,  B82Y10/00 ,  H01L29/0665 ,  H01L29/42392

    摘要： The substrate comprises a first silicon layer, a target layer made from silicon-germanium alloy-base material forming a three-dimensional pattern with first and second securing areas and at least one connecting area. The first silicon layer is tensile stressed and/or the target layer contains carbon atoms. The first silicon layer is eliminated in the connecting area. The target layer of the connecting area is thermally oxidized so as to form the nanowire. The lattice parameter of the first silicon layer is identical to the lattice parameter of the material constituting the suspended beam, after said first silicon layer has been eliminated.

    摘要翻译： 基板包括第一硅层，由硅 - 锗合金基材制成的目标层，其形成具有第一和第二固定区域和至少一个连接区域的三维图案。 第一硅层是拉伸应力的和/或目标层含有碳原子。 在连接区域中消除第一硅层。 连接区域的目标层被热氧化以形成纳米线。 在消除了第一硅层之后，第一硅层的晶格参数与构成悬挂光束的材料的晶格参数相同。

    Method for making asymmetric double-gate transistors by which asymmetric and symmetric double-gate transistors can be made on the same substrate
    6.
    发明授权
    Method for making asymmetric double-gate transistors by which asymmetric and symmetric double-gate transistors can be made on the same substrate 有权
    制造不对称双栅极晶体管的方法，通过该方法可以在同一衬底上制造不对称和对称双栅极晶体管

    公开(公告)号：US08232168B2

    公开(公告)日：2012-07-31

    申请号：US12521311

    申请日：2007-12-28

    申请人： Maud Vinet ,  Olivier Thomas ,  Olivier Rozeau ,  Thierry Poiroux

    发明人： Maud Vinet ,  Olivier Thomas ,  Olivier Rozeau ,  Thierry Poiroux

    IPC分类号： H01L21/336

    CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L27/11 ,  H01L29/78645

    摘要： A method for fabricating a microelectronic device with one or plural double-gate transistors, including: a) forming one or plural structures on a substrate including at least a first block configured to form a first gate of a double-gate transistor, and at least a second block configured to form the second gate of said double-gate, the first block and the second block being located on opposite sides of at least one semiconducting zone and separated from the semiconducting zone by a first gate dielectric zone and a second gate dielectric zone respectively, and b) doping at least one or plural semiconducting zones in the second block of at least one given structure among the structures, using at least one implantation selective relative to the first block, the second block being covered by a hard mask, a critical dimension of the hard mask being larger than the critical dimension of the second block.

    摘要翻译： 一种用于制造具有一个或多个双栅极晶体管的微电子器件的方法，包括：a）在至少包括构成为形成双栅极晶体管的第一栅极的第一块的至少一个衬底上形成一个或多个结构，并且至少 第二块，其被配置为形成所述双栅极的第二栅极，所述第一块和所述第二块位于至少一个半导体区的相对侧上，并且通过第一栅极介电区和第二栅极电介质与所述半导体区分离 并且b）使用相对于第一块选择性的至少一种植入，在所述结构中掺杂至少一个给定结构的第二块中的至少一个或多个半导体区域，所述第二块被硬掩模覆盖， 硬掩模的临界尺寸大于第二块的临界尺寸。

    Method for manufacturing a strained channel MOS transistor
    7.
    发明授权
    Method for manufacturing a strained channel MOS transistor 有权
    制造应变通道MOS晶体管的方法

    公开(公告)号：US08530292B2

    公开(公告)日：2013-09-10

    申请号：US13229081

    申请日：2011-09-09

    申请人： Yves Morand ,  Thierry Poiroux ,  Jean-Charles Barbe

    发明人： Yves Morand ,  Thierry Poiroux ,  Jean-Charles Barbe

    IPC分类号： H01L21/20

    CPC分类号： H01L29/66772 ,  H01L21/76224 ,  H01L21/76283 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7846

    摘要： A method for manufacturing a strained channel MOS transistor including the steps of: forming, at the surface of a semiconductor substrate, a MOS transistor comprising source and drain regions and an insulated sacrificial gate which partly extends over insulation areas surrounding the transistor; forming a layer of a dielectric material having its upper surface level with the upper surface of the sacrificial gate; removing the sacrificial gate; etching at least an upper portion of the exposed insulation areas to form trenches therein; filling the trenches with a material capable of applying a strain to the substrate; and forming, in the space left free by the sacrificial gate, an insulated MOS transistor gate.

    摘要翻译： 一种制造应变通道MOS晶体管的方法，包括以下步骤：在半导体衬底的表面形成包括源极和漏极区域的MOS晶体管和绝缘牺牲栅极，其部分地延伸超过围绕晶体管的绝缘区域; 形成具有其上表面水平的电介质材料层与牺牲栅极的上表面; 去除牺牲门; 蚀刻暴露的绝缘区域的至少上部以在其中形成沟槽; 用能够向基材施加应变的材料填充沟槽; 并且在由牺牲栅极留下的空间中形成绝缘的MOS晶体管栅极。

    FIELD EFFECT TRANSISTOR WITH ALTERNATE ELECTRICAL CONTACTS
    9.
    发明申请
    FIELD EFFECT TRANSISTOR WITH ALTERNATE ELECTRICAL CONTACTS 有权
    具有替代电气接触的场效应晶体管

    公开(公告)号：US20100155843A1

    公开(公告)日：2010-06-24

    申请号：US12665463

    申请日：2008-06-19

    申请人： Frederic Mayer ,  Laurent Clavelier ,  Thierry Poiroux ,  Gerard Billiot

    发明人： Frederic Mayer ,  Laurent Clavelier ,  Thierry Poiroux ,  Gerard Billiot

    IPC分类号： H01L27/12 ,  H01L21/762

    CPC分类号： H01L29/7855 ,  H01L29/41791 ,  H01L29/66795

    摘要： A field effect transistor including: a support layer, a plurality of active zones based on a semiconductor, each active zone configured to form a channel and arranged between two gates adjacent to each other and consecutive, the active zones and the gates being arranged on the support layer, each gate including a first face on the side of the support layer and a second face opposite the first face. The second face of a first of the two gates is electrically connected to a first electrical contact made on the second face of the first of the two gates, and the first face of a second of the two gates is electrically connected to a second electrical contact passing through the support layer. The gates of the transistor are not electrically connected to each other.

    摘要翻译： 一种场效应晶体管，包括：支撑层，基于半导体的多个有源区，每个有源区被配置为形成沟道并且布置在彼此相邻并连续的两个栅极之间，所述有源区和栅极被布置在 支撑层，每个门包括在支撑层侧面的第一面和与第一面相对的第二面。 两个栅极中的第一个的第二面电连接到在两个栅极中的第一个栅极的第二面上形成的第一电触点，并且两个栅极中的第二个的第一面电连接到第二电触点 穿过支撑层。 晶体管的栅极彼此不电连接。