公开(公告)号：US06355564B1

公开(公告)日：2002-03-12

申请号：US09384080

申请日：1999-08-26

申请人： Jeffrey D. Birdsley ,  Matthew Thayer

发明人： Jeffrey D. Birdsley ,  Matthew Thayer

IPC分类号： H01L2166

CPC分类号： G01R31/311 ,  G01N1/32 ,  H01L21/3065

摘要： According to an example embodiment, a semiconductor device having a back side and a circuit side opposite the back side is analyzed. The semiconductor device includes bulk silicon in the back side and also includes epitaxial silicon. An ion gas comprising SF6 and N2 is directed at a target region in the back side. Using the ion gas, the target region in the back side is selectively etched using reactive ion etching (RIE) and an exposed region is formed. The etching is selective to the bulk silicon. When the etching process encounters the epitaxial silicon, the etch rate slows and is used as an endpoint indicator of the selective etching process. Once the etching process is stopped, the circuitry is accessed via the exposed region.

摘要翻译： 根据示例性实施例，分析了具有背侧和与背面相反的电路侧的半导体器件。 半导体器件包括背面的体硅，并且还包括外延硅。 包含SF 6和N 2的离子气体指向后侧的目标区域。 使用离子气体，使用反应离子蚀刻（RIE）来选择性地蚀刻后侧的目标区域，并且形成暴露区域。 蚀刻对体硅有选择性。 当蚀刻工艺遇到外延硅时，蚀刻速率减慢并被用作选择性蚀刻工艺的端点指示器。 一旦蚀刻过程停止，电路就通过暴露的区域被访问。

公开(公告)号：US06294395B1

公开(公告)日：2001-09-25

申请号：US09383791

申请日：1999-08-26

申请人： Jeffrey D. Birdsley ,  Matthew Thayer

发明人： Jeffrey D. Birdsley ,  Matthew Thayer

IPC分类号： H01L2166

CPC分类号： G01R31/316 ,  G01R31/2886 ,  G01R31/311

摘要： Current reactive ion etching (RIE) techniques are not applicable to back side etching of semiconductor devices. According to an example embodiment, the present invention is directed to a method for analyzing a semiconductor device having a back side and a circuit side opposite the back side. An ion gas including SF6 and N2 is directed at a target region in the back side. Using the ion gas, the target region is etched using reactive ion etching (RIE). An exposed region is formed, and circuitry in the device is accessed via the exposed region. The use of the ion gas enables back side RIE that is capable of producing an etched surface that is usable for back side access.

摘要翻译： 电流反应离子蚀刻（RIE）技术不适用于半导体器件的背面蚀刻。 根据示例性实施例，本发明涉及一种用于分析具有背侧和与背面相反的电路侧的半导体器件的方法。 包括SF 6和N 2的离子气体指向背面的目标区域。 使用离子气体，使用反应离子蚀刻（RIE）蚀刻靶区域。 形成暴露区域，并且经由暴露区域访问器件中的电路。 使用离子气体能够实现能够产生可用于背面进入的蚀刻表面的背面RIE。

公开(公告)号：US06850081B1

公开(公告)日：2005-02-01

申请号：US10164506

申请日：2002-06-05

申请人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone

发明人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone

IPC分类号： G01R31/28 ,  G01R31/319 ,  G01R31/303

CPC分类号： G01R31/2884 ,  G01R31/31905

摘要： Semiconductor analysis is improved via the use of fiber optic communications. According to an example embodiment of the present invention, a stimulation device is adapted to stimulate an integrated circuit die, and the die generates a response to the stimulation. An optical signal generator, either incorporated into the die or coupled to the die, detects the response, converts the response to an optical signal and transmits the optical signal. The optical signal is received at a testing arrangement adapted to analyze the die therefrom. The optical signal is used to analyze the die, improving signal quality and the ability to perform high-speed analysis of the die.

摘要翻译： 通过使用光纤通信改进了半导体分析。 根据本发明的示例性实施例，刺激装置适于刺激集成电路管芯，并且管芯产生对刺激的响应。 将光信号发生器并入芯片或耦合到管芯，检测响应，将响应转换为光信号并发送光信号。 光学信号在适于从其分析模具的测试装置处被接收。 光信号用于分析芯片，提高信号质量和对芯片进行高速分析的能力。

公开(公告)号：US06686757B1

公开(公告)日：2004-02-03

申请号：US09409217

申请日：1999-09-30

申请人： Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis ,  Jeffrey D. Birdsley ,  Michael R. Bruce

发明人： Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis ,  Jeffrey D. Birdsley ,  Michael R. Bruce

IPC分类号： G01R3128

CPC分类号： G01R31/311

摘要： According to an example embodiment of the present invention, a defect detection approach involves detecting the existence of defects in an integrated circuit as a function of at least one applied energy source. In response to energy that is applied to the integrated circuit, response signals are detected. A parameter including information such as amplitude, frequency, phase, or a spectrum is developed for a reference integrated circuit device and then compared to the detected response signal. The deviation in the response and reference signals, and the type of energy source used, are correlated to a particular defect in the device.

摘要翻译： 根据本发明的示例性实施例，缺陷检测方法包括检测作为至少一个应用能量源的函数的集成电路中的缺陷的存在。 响应于施加到集成电路的能量，检测响应信号。 为参考集成电路器件开发包括振幅，频率，相位或频谱等信息的参数，然后与检测到的响应信号进行比较。 响应和参考信号的偏差以及所使用的能量源的类型与设备中的特定缺陷相关。

公开(公告)号：US06483327B1

公开(公告)日：2002-11-19

申请号：US09409088

申请日：1999-09-30

申请人： Michael R. Bruce ,  Victoria J. Bruce ,  Jeffrey D. Birdsley ,  Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis

发明人： Michael R. Bruce ,  Victoria J. Bruce ,  Jeffrey D. Birdsley ,  Rosalinda M. Ring ,  Rama R. Goruganthu ,  Brennan V. Davis

IPC分类号： G01R31302

CPC分类号： G01R1/071 ,  G01R31/311

摘要： A method and system providing spatial and timing resolution for photoemission microscopy of an integrated circuit. A microscope having an objective lens forming a focal plane is arranged to view the integrated circuit, and an aperture element having an aperture is optically aligned in the back focal plane of the microscope. The aperture element is positioned for viewing a selected area of the integrated circuit. A position-sensitive avalanche photo-diode is optically aligned with the aperture to detect photoemissions when test signals are applied to the integrated circuit.

摘要翻译： 一种为集成电路的光电显微镜提供空间和时序分辨率的方法和系统。 具有形成焦平面的物镜的显微镜被布置成观看集成电路，并且具有孔的孔径元件在显微镜的后焦平面中被光学对准。 光圈元件被定位成用于观看集成电路的选定区域。 位置敏感的雪崩光电二极管与孔径光学对准以在测试信号被施加到集成电路时检测光电发射。

公开(公告)号：US06430728B1

公开(公告)日：2002-08-06

申请号：US09410147

申请日：1999-09-30

申请人： Rama R. Goruganthu ,  Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring

发明人： Rama R. Goruganthu ,  Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring

IPC分类号： G06F1750

CPC分类号： G01R31/307 ,  G10K15/046

摘要： According to an example embodiment, the present invention is directed to a system and method for analyzing an integrated circuit. A laser is directed to the back side of an integrated circuit and causes local heating, which generates acoustic energy in the circuit. The acoustic energy propagation in the integrated circuit is detected via at least two detectors. Using the detected acoustic energy from the detectors, at least one circuit defect is detected and located.

摘要翻译： 根据示例性实施例，本发明涉及用于分析集成电路的系统和方法。 激光被引导到集成电路的背面，并引起局部加热，其在电路中产生声能。 通过至少两个检测器检测集成电路中的声能传播。 使用来自检测器的检测到的声能，检测和定位至少一个电路缺陷。

公开(公告)号：US06417068B1

公开(公告)日：2002-07-09

申请号：US09247001

申请日：1999-02-08

申请人： Victoria Bruce ,  Susan Li ,  Jeffrey D. Birdsley

发明人： Victoria Bruce ,  Susan Li ,  Jeffrey D. Birdsley

IPC分类号： H01L2176

CPC分类号： H01L23/544 ,  B23K26/0624 ,  H01L23/525 ,  H01L2223/54473 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01077 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2224/05599

摘要： According to one aspect of the disclosure, the present invention provides methods and arrangements for milling the substrate of a semiconductor device and exposing a selected region in the substrate. A laser is directed at a selected area of the back side of the device to create a small marker to be used for alignment during the milling process. The substrate is then milled to expose the selected area within the substrate, using the marker as alignment.

摘要翻译： 根据本公开的一个方面，本发明提供了用于铣削半导体器件的衬底并暴露衬底中的选定区域的方法和布置。 激光被引导到设备背面的选定区域，以产生在铣削过程中用于对准的小标记。 然后将衬底研磨以暴露衬底内的选定区域，使用标记作为对准。

公开(公告)号：US06414335B1

公开(公告)日：2002-07-02

申请号：US09864688

申请日：2001-05-23

申请人： Rama R. Goruganthu ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone ,  Jeffrey D. Birdsley

发明人： Rama R. Goruganthu ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone ,  Jeffrey D. Birdsley

IPC分类号： H01L2358

CPC分类号： G01R31/312 ,  G01R31/307

摘要： Analysis of a semiconductor die having silicon-on-insulator (SOI) structure is enhanced by capacitively coupling a signal to the die. According to an example embodiment of the present invention, a die having a thinned back side is analyzed by capacitively coupling an input signal through the insulator portion of the SOI structure and effecting a state change to circuitry in the die. The state change is used to evaluate a characteristic of the die, such as by detecting a response to the state change. The ability to force such a state change is helpful for evaluating dies having SOI structure, and is particularly useful for evaluation techniques that require or benefit from maintaining the insulator portion of the SOI structure intact.

摘要翻译： 通过将信号电容耦合到管芯来增强具有绝缘体上硅（SOI）结构的半导体管芯的分析。 根据本发明的示例性实施例，通过电容耦合通过SOI结构的绝缘体部分的输入信号并对模具中的电路进行状态分析来分析具有减薄背侧的管芯。 状态变化用于评估管芯的特性，例如通过检测对状态变化的响应。 强制这种状态变化的能力有助于评估具有SOI结构的管芯，并且对于需要或受益于保持SOI结构的绝缘体部分而完整的评估技术特别有用。

公开(公告)号：US07196800B1

公开(公告)日：2007-03-27

申请号：US10205780

申请日：2002-07-26

申请人： Jeffrey D. Birdsley ,  Rama R. Goruganthu ,  Michael R. Bruce

发明人： Jeffrey D. Birdsley ,  Rama R. Goruganthu ,  Michael R. Bruce

IPC分类号： G01B11/02

CPC分类号： G01B11/0683

摘要： A light reflected from a semiconductor die is used for enhanced control of substrate removal from the die. According to an example embodiment of the present invention, light reflected from a semiconductor die as it is undergoing substrate removal is used to detect the progress of the substrate removal process, and the removal process is controlled therefrom. In different embodiments, the reflected light is used to detect the removal of a portion of a layer of material in the die and to detect the removal of an entire layer of material.

摘要翻译： 从半导体管芯反射的光用于增强对从管芯移除衬底的控制。 根据本发明的示例性实施例，使用从正在进行基板去除的半导体管芯反射的光来检测基板去除过程的进程，并且从其中控制去除过程。 在不同的实施例中，反射光用于检测去除模具中的材料层的一部分并检测整个材料层的去除。

公开(公告)号：US06433572B1

公开(公告)日：2002-08-13

申请号：US09378848

申请日：1999-08-23

申请人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Rama R. Goruganthu ,  Brennan Davis ,  Rosalinda M. Ring

发明人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Rama R. Goruganthu ,  Brennan Davis ,  Rosalinda M. Ring

IPC分类号： G01R3128

CPC分类号： G01R31/311

摘要： A system and method for analyzing an integrated circuit device involves generating a magnetic field in circuitry forming a power grid within the integrated circuit device. The magnetic field generator is switched off, and the charge on the power grid dissipates through internal device structures to ground. This decay of the charged power grid is detected and evaluated to assess the quality or consistency of the power distribution grid. Faulty power grids will have a decay pattern that differs from high quality power grids.

摘要翻译： 用于分析集成电路器件的系统和方法涉及在形成集成电路器件内的电网的电路中产生磁场。 磁场发生器关闭，电网上的电荷通过内部器件结构耗散到地。 检测并评估充电电网的这种衰减，以评估配电网的质量或一致性。 电网故障将具有与高品质电网不同的衰减模式。