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11 条记录 (耗时 0.036 秒)

    Accessory device authentication
    2.
    发明授权
    Accessory device authentication 有权
    附件设备认证

    公开(公告)号：US08935774B2

    公开(公告)日：2015-01-13

    申请号：US13471405

    申请日：2012-05-14

    申请人： Jim Tom Belesiu ,  Gene Robert Obie ,  James Charles Marshall ,  Robert D. Young ,  Nathan C. Sherman ,  Edward C. Giaimo, III ,  David Neff ,  Jose R. Sousa

    发明人： Jim Tom Belesiu ,  Gene Robert Obie ,  James Charles Marshall ,  Robert D. Young ,  Nathan C. Sherman ,  Edward C. Giaimo, III ,  David Neff ,  Jose R. Sousa

    IPC分类号： G06F21/00 ,  G06F1/26

    CPC分类号： G06F1/263 ,  G06F1/26

    摘要： Accessory device authentication techniques are described. In one or more embodiments, connection of an accessory device to a host computing device is detected. Responsive to the detection, an authentication sequence may occur to verify an identity and/or capabilities of the accessory device. Upon successful authentication of the accessory device, the host device may authorize the accessory device for power exchange interactions with the host device. The host device may then draw supplemental power from a power source associated with the authorized accessory device, such as a battery or power adapter. The host device may also enable the accessory device to obtain and use power supplied by the host device in some scenarios. Power exchange between a host device and an authorized accessory may be managed in accordance with capabilities of the accessory device that are identified during authentication.

    摘要翻译： 描述了附件设备认证技术。 在一个或多个实施例中，检测附件设备到主计算设备的连接。 响应于检测，可能发生认证序列以验证附件设备的身份和/或能力。 在附件设备成功认证后，主机设备可以授权附件设备进行与主机设备的电力交换交互。 然后，主机设备可以从与授权的附件设备（例如电池或电源适配器）相关联的电源中抽取补充电力。 在某些情况下，主机设备还可以使附件设备能够获得和使用由主机设备提供的功率。 可以根据在认证期间识别的附件设备的能力来管理主机设备和授权配件之间的电力交换。

    Folded dummy world line
    3.
    发明授权
    Folded dummy world line 失效
    折叠虚拟世界线

    公开(公告)号：US5841720A

    公开(公告)日：1998-11-24

    申请号：US918740

    申请日：1997-08-26

    申请人： James J. Covino ,  Alan L. Roberts ,  Jose R. Sousa

    发明人： James J. Covino ,  Alan L. Roberts ,  Jose R. Sousa

    IPC分类号： G11C11/413 ,  G11C7/14 ,  G11C8/18 ,  H01L21/8244 ,  H01L27/10 ,  H01L27/11 ,  G11C7/02

    CPC分类号： G11C8/18 ,  G11C7/14

    摘要： A memory array comprising a number of memory cells, a set path, a signal path, and at least one word line for transmitting a word line select signal to a row of the memory cells. The word line extends from a first driver end to a second end. The memory array further includes a dummy word line extending from the first driver end to a point between the first and second ends and back to the first end for transmitting a tracking signal responsive to the word line select signal. By folding the dummy word line in this manner, improved tracking of the set path with the signal path is achieved.

    摘要翻译： 一种存储器阵列，包括多个存储器单元，设定路径，信号路径以及用于将字线选择信号发送到存储器单元的行的至少一个字线。 字线从第一驱动器端延伸到第二端。 存储器阵列还包括从第一驱动器端延伸到第一端和第二端之间的点并返回到第一端的虚拟字线，用于响应于字线选择信号发送跟踪信号。 通过以这种方式折叠伪字线，实现了具有信号路径的设定路径的改进跟踪。

    Using one memory to supply addresses to an associated memory during testing
    5.
    发明授权
    Using one memory to supply addresses to an associated memory during testing 失效
    在测试期间使用一个内存来提供地址给相关的内存

    公开(公告)号：US5563833A

    公开(公告)日：1996-10-08

    申请号：US398465

    申请日：1995-03-03

    申请人： Robert D. Adams ,  John Connor ,  James J. Covino ,  Roy C. Flaker ,  Garrett S. Koch ,  Alan L. Roberts ,  Jose R. Sousa ,  Luigi Ternullo, Jr.

    发明人： Robert D. Adams ,  John Connor ,  James J. Covino ,  Roy C. Flaker ,  Garrett S. Koch ,  Alan L. Roberts ,  Jose R. Sousa ,  Luigi Ternullo, Jr.

    IPC分类号： G06F12/16 ,  G06F12/08 ,  G11C8/10 ,  G11C15/00 ,  G11C15/04 ,  G11C29/00 ,  G11C29/02 ,  G11C29/10 ,  G11C29/12 ,  G11C29/56 ,  G11C7/00

    CPC分类号： G11C29/12 ,  G06F12/0893 ,  G11C15/00 ,  G11C8/10 ,  G11C29/10

    摘要： An associated memory structure having a plurality of memories amenable for testing and a method of testing the memories is provided. First and second memories are formed, wherein data in the first memory provides a basis for at least a portion of the input to the second memory during functional operation of two memories. Preferably, an output latch for receiving the output test data from the first memory is provided. Means are provided for loading the first memory with data which is utilized as a basis for providing at least a portion of the input to the second memory. An access path from the output port of the first memory to the input port of the second memory allows use of the data in the first memory to generate at least a portion of the input to the second memory. The first memory is first tested independently of the second memory. Thereafter, the first memory is loaded with preconditioned data that is used as a basis for inputs to the second memory during testing of the second memory. The second memory is then tested by generating inputs to the first memory during testing of the second memory. Thus, outputs of the first memory constitute at least a portion of test data inputted to the second memory. A latch is provided to capture the output of the test data from the second memory.

    摘要翻译： 提供了具有适于测试的多个存储器的关联存储器结构和测试存储器的方法。 形成第一和第二存储器，其中在两个存储器的功能操作期间，第一存储器中的数据为至少一部分输入提供基础。 优选地，提供用于从第一存储器接收输出测试数据的输出锁存器。 提供了用于将数据加载到第一存储器的装置，该数据被用作将至少一部分输入提供给第二存储器的基础。 从第一存储器的输出端口到第二存储器的输入端口的访问路径允许使用第一存储器中的数据来生成至第二存储器的输入的至少一部分。 第一个内存首先被独立于第二个内存进行测试。 此后，第一存储器加载预测数据，该预处理数据在第二存储器测试期间用作输入到第二存储器的基础。 然后在测试第二个存储器期间通过产生第一个存储器的输入来测试第二个存储器。 因此，第一存储器的输出构成输入到第二存储器的测试数据的至少一部分。 提供锁存器以捕获来自第二存储器的测试数据的输出。

    MODULAR POLYMERIC EMI/RFI SEAL
    6.
    发明申请
    MODULAR POLYMERIC EMI/RFI SEAL 审中-公开
    模块化POLYMERIC EMI / RFI密封

    公开(公告)号：US20110079962A1

    公开(公告)日：2011-04-07

    申请号：US12897398

    申请日：2010-10-04

    申请人： Donald M. Munro ,  Jon M. Lenhert ,  Karthik Vaideeswaran ,  Jose R. Sousa

    发明人： Donald M. Munro ,  Jon M. Lenhert ,  Karthik Vaideeswaran ,  Jose R. Sousa

    IPC分类号： F16J15/16 ,  F16J15/02 ,  B29C37/00

    CPC分类号： F16J15/3212 ,  F16J15/3236

    摘要： A seal includes a seal body including an annular cavity, and an annular spring within the annular cavity. The seal body, the seal body includes a composite material having a thermoplastic material and a filler. The composite material can have a Young's Modulus of at least about 0.5 GPa, a volume resistitivity of not greater than about 200 Ohm-cm, an elongation of at least about 20%, a surface resistitivity of not greater than about 104 Ohm/sq, or any combination thereof.

    摘要翻译： 密封件包括包括环形空腔的密封体和环形空腔内的环形弹簧。 密封体，密封体包括具有热塑性材料和填料的复合材料。 复合材料可以具有至少约0.5GPa的杨氏模量，不大于约200欧姆 - 厘米的体积电阻率，至少约20％的伸长率，不大于约104欧姆/平方厘米的表面电阻率， 或其任何组合。

    POLYMERS WITH METAL FILLER FOR EMI SHIELDING
    8.
    发明申请
    POLYMERS WITH METAL FILLER FOR EMI SHIELDING 审中-公开
    具有金属填料的聚合物用于EMI屏蔽

    公开(公告)号：US20120177906A1

    公开(公告)日：2012-07-12

    申请号：US13336535

    申请日：2011-12-23

    申请人： Jose R. Sousa ,  Jon M. Lenhert ,  Chan S. Chung

    发明人： Jose R. Sousa ,  Jon M. Lenhert ,  Chan S. Chung

    IPC分类号： B32B27/04

    CPC分类号： H05K9/0083 ,  C08J5/041 ,  C08J2327/18 ,  H05K9/0015 ,  Y10T428/24994

    摘要： A composite material includes a thermoplastic material, and a metallic filler dispersed within the thermoplastic material. The metallic filler may be fibrous, particulate or a combination thereof. The metallic filler may have a length in a range of about 3 mm to about 10 mm, and/or a mean particle size of about 2 microns to about 10 microns. The composite material may have a volumetric resistivity of not greater than about 0.5 Ohm·cm. The composite material can be in the form of a sealing component.

    摘要翻译： 复合材料包括热塑性材料和分散在热塑性材料内的金属填料。 金属填料可以是纤维状，颗粒状或其组合。 金属填料的长度可以在约3mm至约10mm的范围内，和/或约2微米至约10微米的平均粒度。 复合材料的体积电阻率可以不大于约0.5欧姆·厘米。 复合材料可以是密封组件的形式。

    Hydrangea plant named `Ravel`
    9.
    植物专利
    Hydrangea plant named `Ravel` 失效

    公开(公告)号：USPP10152P

    公开(公告)日：1997-12-16

    申请号：US675780

    申请日：1996-07-05

    申请人： Jose R. Sousa

    发明人： Jose R. Sousa

    摘要： This invention relates to a new and distinct cultivar of Hydrangea macrophylla (Thunb.) named `Ravel` which originated as a sport from the inventor's controlled commercial growing of the non-patented Hydrangea macrophylla cultivar `Merritts Supreme`, and is distinguished from its parent by the unique pigmentation pattern which causes the florets and inflorescence to be both pink and white, and gives each floret a white center and four pink fan-shaped points at the outer edges, resulting in a pink and white flower at the peak of its bloom, not predominantly a pink flower. The new variety `Ravel` further possesses the favorable characteristics of: agressive, compact growth habit; long lasting large flowers and the ability to be easily forced in a greenhouse for flowering in the spring.

    Address buffer for synchronous system
    10.
    发明授权
    Address buffer for synchronous system 失效
    同步系统地址缓冲区

    公开(公告)号：US5625302A

    公开(公告)日：1997-04-29

    申请号：US598304

    申请日：1996-02-08

    申请人： James J. Covino ,  Jose R. Sousa

    发明人： James J. Covino ,  Jose R. Sousa

    IPC分类号： H03K17/693 ,  H03K19/096

    CPC分类号： H03K17/693

    摘要： A truc/complement receiver driver circuit in which the input signals may be applied prior to a sysnchronous clock signal. The input signals are sensed and latched to generate complementary output signals. The generation of the output signals causes the receiver portion of the circuit to be automatically reset for the next cycle. The leading edge of the systemclock causes the circuit outputs to reset and enables the receiver circuit to be enabled for the next cycle. Multiplexed input receiver circuits allow the circuit to respond to a plurality of input signal sources.

    摘要翻译： 一个truc /补码接收器驱动器电路，其中可以在系统同步时钟信号之前施加输入信号。 输入信号被感测和锁存以产生互补的输出信号。 输出信号的产生使得电路的接收器部分在下一个周期中自动复位。 系统时钟的前沿使得电路输出复位，并使接收器电路在下一个周期中使能。 复用输入接收器电路允许电路响应于多个输入信号源。