公开(公告)号：US20080113503A1

公开(公告)日：2008-05-15

申请号：US11930220

申请日：2007-10-31

申请人： Jin Yuan Lee ,  Ming Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

发明人： Jin Yuan Lee ,  Ming Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

IPC分类号： H01L21/441

CPC分类号： H04B1/7113 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/14 ,  H01L24/15 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/1147 ,  H01L2224/11831 ,  H01L2224/11901 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H04B1/712 ,  H01L2224/13099 ,  H01L2924/00

摘要： The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.

公开(公告)号：US07338890B2

公开(公告)日：2008-03-04

申请号：US11136650

申请日：2005-05-24

申请人： Jin Yuan Lee ,  Ming-Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

发明人： Jin Yuan Lee ,  Ming-Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

IPC分类号： H01L21/44

CPC分类号： H01L24/12 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/525 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/85399 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H04B1/712 ,  H05K3/108 ,  H05K3/243 ,  H05K3/3473 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2201/0949 ,  H05K2203/043 ,  H05K2203/054 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.

公开(公告)号：US08481418B2

公开(公告)日：2013-07-09

申请号：US11930220

申请日：2007-10-31

申请人： Jin-Yuan Lee ,  Ming-Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

发明人： Jin-Yuan Lee ,  Ming-Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

IPC分类号： H01L21/44

CPC分类号： H04B1/7113 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/14 ,  H01L24/15 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/1147 ,  H01L2224/11831 ,  H01L2224/11901 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H04B1/712 ,  H01L2224/13099 ,  H01L2924/00

摘要： The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.

摘要翻译： 本发明提供了一种新的方法和芯片级封装。 本发明从提供接触点的基底开始，接触点通过在钝化层中形成的开口和聚合物或弹性体层暴露。 形成屏障/种子层，产生第一光致抗蚀剂掩模，暴露阻挡层/籽晶层，其中该层覆盖在接触焊盘上，并与其邻接，在与接触焊盘相邻的表面区域上并且沿一个方向从 接触垫 电镀/种子层的暴露表面被电镀以产生互连迹线。 从阻挡层/种子层的表面去除第一光致抗蚀剂掩模。 产生限定焊料凸块的第二光致抗蚀剂掩模产生暴露与接触焊盘相邻并且在一个方向上从接触焊盘发出的势垒/种子层的表面积。 根据第二光致抗蚀剂掩模产生焊料凸块，从阻挡层/种子层的表面去除第二光致抗蚀剂掩模，用覆盖在阻挡层/种子层上的金属电镀暴露电镀和阻挡层/籽晶层。 根据由电镀形成的图案蚀刻暴露的阻挡层/籽晶层，任选地进行焊料凸点的回流。

公开(公告)号：US20100038803A9

公开(公告)日：2010-02-18

申请号：US11930210

申请日：2007-10-31

申请人： Jin-Yuan Lee ,  Ming-Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

发明人： Jin-Yuan Lee ,  Ming-Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

IPC分类号： H01L23/52

CPC分类号： H01L24/12 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/525 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/85399 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H04B1/712 ,  H05K3/108 ,  H05K3/243 ,  H05K3/3473 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2201/0949 ,  H05K2203/043 ,  H05K2203/054 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.

摘要翻译： 本发明提供了一种新的方法和芯片级封装。 本发明从提供接触点的基底开始，接触点通过在钝化层中形成的开口和聚合物或弹性体层暴露。 形成屏障/种子层，产生第一光致抗蚀剂掩模，暴露阻挡层/籽晶层，其中该层覆盖在接触焊盘上，并与其邻接，在与接触焊盘相邻的表面区域上并且沿一个方向从 接触垫 电镀/种子层的暴露表面被电镀以产生互连迹线。 从阻挡层/种子层的表面去除第一光致抗蚀剂掩模。 产生限定焊料凸块的第二光致抗蚀剂掩模产生暴露与接触焊盘相邻并且在一个方向上从接触焊盘发出的势垒/种子层的表面积。 根据第二光致抗蚀剂掩模产生焊料凸块，从阻挡层/种子层的表面去除第二光致抗蚀剂掩模，用覆盖在阻挡层/种子层上的金属电镀暴露电镀和阻挡层/籽晶层。 根据由电镀形成的图案蚀刻暴露的阻挡层/籽晶层，任选地进行焊料凸点的回流。

公开(公告)号：US20090137110A9

公开(公告)日：2009-05-28

申请号：US11930220

申请日：2007-10-31

申请人： Jin Yuan Lee ,  Ming Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

发明人： Jin Yuan Lee ,  Ming Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

IPC分类号： H01L21/441

CPC分类号： H04B1/7113 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/14 ,  H01L24/15 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/1147 ,  H01L2224/11831 ,  H01L2224/11901 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H04B1/712 ,  H01L2224/13099 ,  H01L2924/00

摘要： The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.

摘要翻译： 本发明提供了一种新的方法和芯片级封装。 本发明从提供接触点的基底开始，接触点通过在钝化层中形成的开口和聚合物或弹性体层暴露。 形成屏障/种子层，产生第一光致抗蚀剂掩模，暴露阻挡层/籽晶层，其中该层覆盖在接触焊盘上，并与其邻接，在与接触焊盘相邻的表面区域上并且沿一个方向从 接触垫 电镀/种子层的暴露表面被电镀以产生互连迹线。 从阻挡层/种子层的表面去除第一光致抗蚀剂掩模。 产生限定焊料凸块的第二光致抗蚀剂掩模产生暴露与接触焊盘相邻并且在一个方向上从接触焊盘发出的势垒/种子层的表面积。 根据第二光致抗蚀剂掩模产生焊料凸块，从阻挡层/种子层的表面去除第二光致抗蚀剂掩模，用覆盖在阻挡层/种子层上的金属电镀暴露电镀和阻挡层/籽晶层。 根据由电镀形成的图案蚀刻暴露的阻挡层/籽晶层，任选地进行焊料凸点的回流。

公开(公告)号：US20080099928A1

公开(公告)日：2008-05-01

申请号：US11930210

申请日：2007-10-31

申请人： Jin-Yuan Lee ,  Ming-Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

发明人： Jin-Yuan Lee ,  Ming-Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

IPC分类号： H01L23/52

CPC分类号： H01L24/12 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/525 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/85399 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H04B1/712 ,  H05K3/108 ,  H05K3/243 ,  H05K3/3473 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2201/0949 ,  H05K2203/043 ,  H05K2203/054 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.

公开(公告)号：US06642136B1

公开(公告)日：2003-11-04

申请号：US09953525

申请日：2001-09-17

申请人： Jin Yuan Lee ,  Ming Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

发明人： Jin Yuan Lee ,  Ming Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

IPC分类号： H01L2144

CPC分类号： H01L24/12 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/525 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/85399 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H04B1/712 ,  H05K3/108 ,  H05K3/243 ,  H05K3/3473 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2201/0949 ,  H05K2203/043 ,  H05K2203/054 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： A new method and chip scale package is provided. A point of electrical contact over a substrate is exposed through an opening created through overlying layers of passivation and polymer or elastomer, deposited over the substrate. A barrier/seed layer is deposited. A first photoresist mask exposes the barrier/seed layer where this layer overlies and is adjacent to the contact pad. The exposed surface of the barrier/seed layer is electroplated. The first photoresist mask is removed, a second photoresist mask is created to define the solder bump exposing a surface area of the barrier/seed layer not overlying the contact pad. The solder bump is created, the second photoresist mask is removed. The exposed barrier/seed layer is etched in accordance with the electroplating, reflow of the solder bump is optionally performed.

摘要翻译： 提供了一种新的方法和芯片级封装。 衬底上的电接触点通过沉积在衬底上的钝化层和聚合物或弹性体的上层形成的开口露出。 屏障/种子层被沉积。 第一光致抗蚀剂掩模将该层覆盖并与接触垫相邻的势垒/种子层暴露。 屏蔽/种子层的暴露表面被电镀。 去除第一光致抗蚀剂掩模，产生第二光致抗蚀剂掩模以限定暴露阻挡层/种子层的表面积而不覆盖接触焊盘的焊料凸块。 产生焊料凸点，去除第二光致抗蚀剂掩模。 根据电镀蚀刻暴露的阻挡层/籽晶层，任选地进行焊料凸块的回流焊。

公开(公告)号：US20080113504A1

公开(公告)日：2008-05-15

申请号：US11930224

申请日：2007-10-31

申请人： Jin-Yuan Lee ,  Ming-Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

发明人： Jin-Yuan Lee ,  Ming-Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

IPC分类号： H01L21/441

CPC分类号： H04B1/7113 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/14 ,  H01L24/15 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/1147 ,  H01L2224/11831 ,  H01L2224/11901 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H04B1/712 ,  H01L2224/13099 ,  H01L2924/00

摘要： The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.

公开(公告)号：US20080111236A1

公开(公告)日：2008-05-15

申请号：US11930213

申请日：2007-10-31

申请人： Jin-Yuan Lee ,  Ming-Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

发明人： Jin-Yuan Lee ,  Ming-Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

IPC分类号： H01L23/488

CPC分类号： H04B1/7113 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3128 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/14 ,  H01L24/15 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/1147 ,  H01L2224/11831 ,  H01L2224/11901 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H04B1/712 ,  H01L2224/13099 ,  H01L2924/00

摘要： The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.

摘要翻译： 本发明提供了一种新的方法和芯片级封装。 本发明从提供接触点的基底开始，接触点通过在钝化层中形成的开口和聚合物或弹性体层暴露。 形成屏障/种子层，产生第一光致抗蚀剂掩模，暴露阻挡层/籽晶层，其中该层覆盖在接触焊盘上，并与其邻接，在与接触焊盘相邻的表面区域上并且沿一个方向从 接触垫 电镀/种子层的暴露表面被电镀以产生互连迹线。 从阻挡层/种子层的表面去除第一光致抗蚀剂掩模。 产生限定焊料凸块的第二光致抗蚀剂掩模产生暴露与接触焊盘相邻并且在一个方向上从接触焊盘发出的势垒/种子层的表面积。 根据第二光致抗蚀剂掩模产生焊料凸块，从阻挡层/种子层的表面去除第二光致抗蚀剂掩模，用覆盖在阻挡层/种子层上的金属电镀暴露电镀和阻挡层/籽晶层。 根据由电镀形成的图案蚀刻暴露的阻挡层/籽晶层，任选地进行焊料凸点的回流。

公开(公告)号：US07355288B2

公开(公告)日：2008-04-08

申请号：US11120234

申请日：2005-05-02

申请人： Jin Yuan Lee ,  Ming Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

发明人： Jin Yuan Lee ,  Ming Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/12 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/525 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/85399 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H04B1/712 ,  H05K3/108 ,  H05K3/243 ,  H05K3/3473 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2201/0949 ,  H05K2203/043 ,  H05K2203/054 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.

摘要翻译： 本发明提供了一种新的方法和芯片级封装。 本发明从提供接触点的基底开始，接触点通过在钝化层中形成的开口和聚合物或弹性体层暴露。 形成屏障/种子层，产生第一光致抗蚀剂掩模，暴露阻挡层/籽晶层，其中该层覆盖在接触焊盘上，并与其邻接，在与接触焊盘相邻的表面区域上并且沿一个方向从 接触垫 电镀/种子层的暴露表面被电镀以产生互连迹线。 从阻挡层/种子层的表面去除第一光致抗蚀剂掩模。 产生限定焊料凸块的第二光致抗蚀剂掩模产生暴露与接触焊盘相邻并且在一个方向上从接触焊盘发出的势垒/种子层的表面积。 根据第二光致抗蚀剂掩模产生焊料凸块，从阻挡层/种子层的表面去除第二光致抗蚀剂掩模，用覆盖在阻挡层/种子层上的金属电镀暴露电镀和阻挡层/籽晶层。 根据由电镀形成的图案蚀刻暴露的阻挡层/籽晶层，任选地进行焊料凸点的回流。