公开(公告)号：US09281414B2

公开(公告)日：2016-03-08

申请号：US14151288

申请日：2014-01-09

申请人： Jin-Yeon Won ,  Joon-Hee Lee ,  Seung-Woo Paek ,  Dong-Seog Eun

发明人： Jin-Yeon Won ,  Joon-Hee Lee ,  Seung-Woo Paek ,  Dong-Seog Eun

IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L29/66

CPC分类号： H01L29/42344 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： According to example embodiments of inventive concepts, a semiconductor device includes: a substrate, and a stacked structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate. The stacked structure defines a through-hole over the substrate. The gate electrodes each include a first portion between the through-hole and a second portion of the gate electrodes. A channel pattern may be in the through-hole. A tunneling layer may surround the channel pattern. A charge trap layer may surround the tunneling layer, and protective patterns may surround the first portions of the gate electrodes. The protective patterns may be between the first portions of the gate electrodes and the charge trap layer.

摘要翻译： 根据本发明构思的示例性实施例，半导体器件包括：衬底，以及包括层间绝缘层和交替层叠在衬底上的栅电极的堆叠结构。 堆叠结构在衬底上限定通孔。 栅电极各自包括在通孔和栅电极的第二部分之间的第一部分。 通道图案可以在通孔中。 隧道层可围绕通道图案。 电荷陷阱层可围绕隧道层，并且保护图案可围绕栅电极的第一部分。 保护图案可以在栅电极的第一部分和电荷陷阱层之间。

公开(公告)号：US09640549B2

公开(公告)日：2017-05-02

申请号：US14534181

申请日：2014-11-06

申请人： Seok-Won Lee ,  Joon-Hee Lee ,  Dong-Seog Eun ,  Chang-Hyun Lee

发明人： Seok-Won Lee ,  Joon-Hee Lee ,  Dong-Seog Eun ,  Chang-Hyun Lee

IPC分类号： H01L27/115 ,  H01L27/11582 ,  H01L27/11556 ,  G11C5/06 ,  H01L27/11548 ,  H01L27/11575 ,  G11C8/14 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11582 ,  G11C5/063 ,  G11C8/14 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： A vertical memory device includes a substrate, a channel, gate lines and a connecting portion. A plurality of the channels extend in a first direction which is vertical to a top surface of a substrate. A plurality of the gate lines are stacked in the first direction to be spaced apart from each other and extend in a second, lengthwise direction, each gate line intersecting a set of channels and surrounding outer sidewalls of each channel of the set of channels. The gate lines forms a stepped structure which includes a plurality of vertical levels. A connecting portion connects a group of gate lines of the plurality of gate lines located at the same vertical level, the connecting portion diverging from the second direction in which the gate lines of the group of gate lines extend.

公开(公告)号：US20180033799A1

公开(公告)日：2018-02-01

申请号：US15455778

申请日：2017-03-10

申请人： Kohji KANAMORI ,  Dong-Seog Eun

发明人： Kohji KANAMORI ,  Dong-Seog Eun

IPC分类号： H01L27/11582 ,  H01L27/1157

CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

摘要： Disclosed are vertical memory devices and methods of manufacturing the same. The vertical memory device may include includes a substrate, a gate stack structure and channel structure on the substrate, and a charge trap structure between the gate stack structure and the channel structure. The gate stack structure includes conductive structures and insulation interlayer structures that are alternately stacked on each other in a vertical direction on the substrate such that cell regions and inter-cell regions are alternately arranged in the vertical direction. The channel structure penetrates through the gate stack structure in the vertical direction. The charge trap structure and the conductive structures define memory cells at the cell regions. The charge structure is configured to selectively store charges. The charge trap structure includes an anti-coupling structure in the inter-cell region for reducing a coupling between neighboring memory cells adjacent to each other in the vertical direction.

公开(公告)号：US20090029520A1

公开(公告)日：2009-01-29

申请号：US12176618

申请日：2008-07-21

申请人： Dong-Won CHANG ,  Sung-Nam Chang ,  Seung-Gun Seo ,  Dong-Seog Eun

发明人： Dong-Won CHANG ,  Sung-Nam Chang ,  Seung-Gun Seo ,  Dong-Seog Eun

IPC分类号： H01L21/762 ,  H01L21/28

CPC分类号： H01L21/76224 ,  H01L27/11521 ,  H01L27/11524

摘要： A method of forming a semiconductor device, where the method may include forming a first trench in a semiconductor substrate, forming first device isolation patterns that fill the first trench, forming spacers on sidewalls of the first device isolation patterns, forming a second trench in the semiconductor substrate between first device isolation patterns, and forming second device isolation patterns that fill the second trench. The second trench is formed using an etching process adopting the first device isolation pattern and the spacer as a mask.

摘要翻译： 一种形成半导体器件的方法，其中所述方法可以包括在半导体衬底中形成第一沟槽，形成填充第一沟槽的第一器件隔离图案，在第一器件隔离图案的侧壁上形成间隔物，在第二沟槽中形成第二沟槽 半导体衬底在第一器件隔离图案之间，以及形成填充第二沟槽的第二器件隔离图案。 使用采用第一器件隔离图案和间隔物作为掩模的蚀刻工艺形成第二沟槽。

公开(公告)号：US20080124866A1

公开(公告)日：2008-05-29

申请号：US11670546

申请日：2007-02-02

申请人： Dong-Seog Eun ,  Sung-Nam Chang

发明人： Dong-Seog Eun ,  Sung-Nam Chang

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11568

摘要： Methods of forming an integrated circuit device include forming first and second device isolation regions at side-by-side locations within a semiconductor substrate to thereby define a semiconductor active region therebetween. These first and second device isolation regions have sidewalls that extend vertically relative to the semiconductor active region. A first gate insulating layer is formed on a surface of the semiconductor active region. A central portion of the first gate insulating layer extending opposite the semiconductor active region is thinned to thereby define gate insulating residues extending adjacent sidewalls of the first and second device isolation regions. A second gate insulating layer is formed on the gate insulating residues to thereby yield a non-uniformly thick third gate insulating layer. A gate electrode is formed on the non-uniformly thick third gate insulating layer.

摘要翻译： 形成集成电路器件的方法包括在半导体衬底内的并排位置处形成第一和第二器件隔离区域，从而在其间限定半导体有源区。 这些第一和第二器件隔离区域具有相对于半导体有源区域垂直延伸的侧壁。 第一栅绝缘层形成在半导体有源区的表面上。 与半导体有源区相对延伸的第一栅极绝缘层的中心部分变薄，从而限定延伸第一和第二器件隔离区相邻侧壁的栅极绝缘残余物。 在栅极绝缘残渣上形成第二栅极绝缘层，从而产生非均匀厚度的第三栅极绝缘层。 在非均匀厚度的第三栅极绝缘层上形成栅电极。

公开(公告)号：US20060154419A1

公开(公告)日：2006-07-13

申请号：US11327321

申请日：2006-01-09

申请人： Dong-Seog Eun ,  Sung-Hun Lee

发明人： Dong-Seog Eun ,  Sung-Hun Lee

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of fabricating a flash memory device produces a device that has a small cell area and yet a high coupling ratio. First, a basic structure is provided that includes a substrate, a field isolation film protruding from the substrate, and floating gates disposed on the substrate on opposite sides of the floating gate. A first etch process is performed to remove a portion of the field isolation film and thereby expose upper portions of the floating gates. Then, a second etch process is performed to knock off the edges of the floating gates. Thus, a large amount of space is secured between the floating gates for a dielectric film and a control gate.

摘要翻译： 制造闪速存储器件的方法产生具有小单元面积并且具有高耦合比的器件。 首先，提供了一种基本结构，其包括基板，从基板突出的场隔离膜以及在浮动栅极的相对侧上设置在基板上的浮动栅极。 执行第一蚀刻工艺以去除场隔离膜的一部分，从而暴露浮栅的上部。 然后，执行第二蚀刻处理以敲除浮动栅极的边缘。 因此，在用于电介质膜的浮动栅极和控制栅极之间确保了大量的空间。

公开(公告)号：US07736989B2

公开(公告)日：2010-06-15

申请号：US12176618

申请日：2008-07-21

申请人： Dong-Won Chang ,  Sung-Nam Chang ,  Seung-Gun Seo ,  Dong-Seog Eun

发明人： Dong-Won Chang ,  Sung-Nam Chang ,  Seung-Gun Seo ,  Dong-Seog Eun

IPC分类号： H01L21/762 ,  H01L21/28

CPC分类号： H01L21/76224 ,  H01L27/11521 ,  H01L27/11524

摘要： A method of forming a semiconductor device, where the method may include forming a first trench in a semiconductor substrate, forming first device isolation patterns that fill the first trench, forming spacers on sidewalls of the first device isolation patterns, forming a second trench in the semiconductor substrate between first device isolation patterns, and forming second device isolation patterns that fill the second trench. The second trench is formed using an etching process adopting the first device isolation pattern and the spacer as a mask.

摘要翻译： 一种形成半导体器件的方法，其中所述方法可以包括在半导体衬底中形成第一沟槽，形成填充第一沟槽的第一器件隔离图案，在第一器件隔离图案的侧壁上形成间隔物，在第二沟槽中形成第二沟槽 半导体衬底在第一器件隔离图案之间，以及形成填充第二沟槽的第二器件隔离图案。 使用采用第一器件隔离图案和间隔物作为掩模的蚀刻工艺形成第二沟槽。

公开(公告)号：US07348267B2

公开(公告)日：2008-03-25

申请号：US11327321

申请日：2006-01-09

申请人： Dong-Seog Eun ,  Sung-Hun Lee

发明人： Dong-Seog Eun ,  Sung-Hun Lee

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A method of fabricating a flash memory device produces a device that has a small cell area and yet a high coupling ratio. First, a basic structure is provided that includes a substrate, a field isolation film protruding from the substrate, and floating gates disposed on the substrate on opposite sides of the floating gate. A first etch process is performed to remove a portion of the field isolation film and thereby expose upper portions of the floating gates. Then, a second etch process is performed to knock off the edges of the floating gates. Thus, a large amount of space is secured between the floating gates for a dielectric film and a control gate.

摘要翻译： 制造闪速存储器件的方法产生具有小单元面积并且具有高耦合比的器件。 首先，提供了一种基本结构，其包括基板，从基板突出的场隔离膜以及在浮动栅极的相对侧上设置在基板上的浮动栅极。 执行第一蚀刻工艺以去除场隔离膜的一部分，从而暴露浮栅的上部。 然后，执行第二蚀刻处理以敲除浮动栅极的边缘。 因此，在用于电介质膜的浮动栅极和控制栅极之间确保了大量的空间。

公开(公告)号：US06737335B2

公开(公告)日：2004-05-18

申请号：US10440806

申请日：2003-05-19

申请人： Jung-Dal Choi ,  Kyu-Charn Park ,  Dong-Seog Eun

发明人： Jung-Dal Choi ,  Kyu-Charn Park ,  Dong-Seog Eun

IPC分类号： H01L2176

CPC分类号： H01L27/11526 ,  H01L21/76229 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/11541 ,  Y10S438/981

摘要： A shallow trench isolation type semiconductor device includes a gate insulating layer formed in a first region and in a second region. The gate insulating layer is of greater thickness in the first region, relative to the thickness of the gate insulating layer in the second region. A shallow trench isolation layer is also formed in the first region and the second region, the shallow trench isolation layer in the first region being thinner than shallow trench isolation layer in the second region.

摘要翻译： 浅沟槽隔离型半导体器件包括在第一区域和第二区域中形成的栅极绝缘层。 栅极绝缘层相对于第二区域中的栅极绝缘层的厚度在第一区域中具有更大的厚度。 在第一区域和第二区域中还形成浅沟槽隔离层，第一区域中的浅沟槽隔离层比第二区域中的浅沟槽隔离层更薄。

公开(公告)号：US10396092B2

公开(公告)日：2019-08-27

申请号：US15455778

申请日：2017-03-10

申请人： Kohji Kanamori ,  Dong-Seog Eun

发明人： Kohji Kanamori ,  Dong-Seog Eun

IPC分类号： H01L27/00 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

摘要： Disclosed are vertical memory devices and methods of manufacturing the same. The vertical memory device may include includes a substrate, a gate stack structure and channel structure on the substrate, and a charge trap structure between the gate stack structure and the channel structure. The gate stack structure includes conductive structures and insulation interlayer structures that are alternately stacked on each other in a vertical direction on the substrate such that cell regions and inter-cell regions are alternately arranged in the vertical direction. The channel structure penetrates through the gate stack structure in the vertical direction. The charge trap structure and the conductive structures define memory cells at the cell regions. The charge structure is configured to selectively store charges. The charge trap structure includes an anti-coupling structure in the inter-cell region for reducing a coupling between neighboring memory cells adjacent to each other in the vertical direction.