公开(公告)号：US20130320446A1

公开(公告)日：2013-12-05

申请号：US13576933

申请日：2012-07-18

申请人： Wei Wang ,  Jing Wang ,  Lei Guo

发明人： Wei Wang ,  Jing Wang ,  Lei Guo

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/02521 ,  H01L21/0237 ,  H01L21/02488 ,  H01L29/045 ,  H01L29/7849 ,  H01L29/78603

摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a semiconductor substrate; a rare earth oxide layer formed on the semiconductor substrate; a channel region formed on the rare earth oxide layer; and a source region and a drain region formed at both sides of the channel region respectively, in which a relationship between a lattice constant a of the rare earth oxide layer and a lattice constant b of a semiconductor material of the channel region and/or the source region and the drain region is a=(n±c)b, where n is an integer, c is a mismatch ratio of lattice constants, and 0

摘要翻译： 提供半导体结构及其形成方法。 半导体结构包括：半导体衬底; 形成在半导体衬底上的稀土氧化物层; 形成在稀土氧化物层上的沟道区; 以及源极区域和漏极区域，分别形成在沟道区域的两侧，其中稀土氧化物层的晶格常数a与沟道区域的半导体材料的晶格常数b之间的关系和/或 源极区和漏极区是a =（n±c）b，其中n是整数，c是晶格常数的失配比，0

公开(公告)号：US08546857B1

公开(公告)日：2013-10-01

申请号：US13576937

申请日：2012-07-16

申请人： Jing Wang ,  Lei Guo ,  Wei Wang

发明人： Jing Wang ,  Lei Guo ,  Wei Wang

IPC分类号： H01L29/08 ,  H01L29/417 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/0653 ,  H01L29/66636 ,  H01L29/7848

摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a semiconductor substrate; a source region and a drain region defined in the semiconductor substrate respectively, and a trench formed in the source region and/or the drain region, in which a rare earth oxide layer is formed in the trench; a source and/or a drain formed on the rare earth oxide layer; and a channel region formed between the source and the drain. A relationship between a lattice constant a of the rare earth oxide layer and a lattice constant b of a semiconductor material of the source and/or the drain and/or the channel region is a=(n±c)b, where n is an integer, c is a mismatch ratio of lattice constants, and 0

摘要翻译： 提供半导体结构及其形成方法。 半导体结构包括：半导体衬底; 限定在半导体衬底中的源极区和漏极区，以及在沟道中形成有稀土氧化物层的源极区和/或漏极区中形成的沟槽; 在稀土氧化物层上形成的源极和/或漏极; 以及形成在源极和漏极之间的沟道区域。 源极和/或漏极和/或沟道区的半导体材料的稀土氧化物层的晶格常数a与晶格常数b之间的关系为a =（n±c）b，其中n为 整数，c是晶格常数的失配比，0

公开(公告)号：US20130240958A1

公开(公告)日：2013-09-19

申请号：US13521051

申请日：2012-05-29

申请人： Jing Wang ,  Lei Guo ,  Wei Wang

发明人： Jing Wang ,  Lei Guo ,  Wei Wang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/76283 ,  H01L29/7846

摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a semiconductor substrate; an active region formed in the semiconductor substrate, in which the active region comprises: a channel region, and a source region and a drain region formed on both sides of the channel region respectively; and a first isolation trench formed in the semiconductor substrate and on both sides of the active region, in which a first rare earth oxide layer is formed in each first isolation trench to produce a stress in the channel region in a channel length direction.

摘要翻译： 提供半导体结构及其形成方法。 半导体结构包括：半导体衬底; 形成在所述半导体衬底中的有源区，其中所述有源区包括：沟道区，以及分别形成在所述沟道区两侧的源区和漏区; 以及形成在所述半导体衬底中并且在所述有源区的两侧上形成的第一隔离沟槽，其中在每个第一隔离沟槽中形成第一稀土氧化物层，以在沟道长度方向上的沟道区域中产生应力。

公开(公告)号：US20130320413A1

公开(公告)日：2013-12-05

申请号：US13576934

申请日：2012-07-18

申请人： Wei Wang ,  Jing Wang ,  Lei Guo

发明人： Wei Wang ,  Jing Wang ,  Lei Guo

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78603 ,  H01L29/7849 ,  H01L29/78654 ,  H01L29/78681 ,  H01L29/78684

摘要： A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a semiconductor substrate; a trench formed in the semiconductor substrate, in which a rare earth oxide layer is formed in the trench; a channel region partly or entirely formed on the rare earth oxide layer; and a source region and a drain region formed at both sides of the channel region, respectively. A relationship between a lattice constant a of the rare earth oxide layer and a lattice constant b of a semiconductor material of the channel region and/or the source region and the drain region is a=(n±c)b, where n is an integer, c is a mismatch ratio of lattice constants, and 0

摘要翻译： 提供半导体结构及其形成方法。 半导体结构包括：半导体衬底; 形成在半导体衬底中的沟槽，其中在沟槽中形成稀土氧化物层; 部分或全部形成在稀土氧化物层上的沟道区; 以及分别形成在沟道区两侧的源区和漏区。 稀土氧化物层的晶格常数a与沟道区域和/或源极区域和漏极区域的半导体材料的晶格常数b之间的关系为a =（n±c）b，其中n为 整数，c是晶格常数的失配比，0

公开(公告)号：US20120025279A1

公开(公告)日：2012-02-02

申请号：US13132760

申请日：2011-05-10

申请人： Jing Wang ,  Wei Wang ,  Lei Guo ,  Jun Xu

发明人： Jing Wang ,  Wei Wang ,  Lei Guo ,  Jun Xu

IPC分类号： H01L29/812 ,  H01L21/338

CPC分类号： H01L29/66636 ,  H01L29/0895 ,  H01L29/1054 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/66643 ,  H01L29/78 ,  H01L29/7839

摘要： A low Schottky barrier semiconductor structure is provided, comprising: a substrate; a SiGe layer with low Ge content formed on the substrate; a channel layer with high Ge content formed on the SiGe layer; a gate stack formed on the substrate and a side wall of one or more layers formed on both sides of the gate stack; a metal source and a metal drain formed in the channel layer and on the both sides of the gate stack respectively; and an insulation layer formed between the substrate and the metal source and between the substrate and the metal drain respectively.

摘要翻译： 提供了一种低肖特基势垒半导体结构，包括：衬底; 在基板上形成具有低Ge含量的SiGe层; 在SiGe层上形成具有高Ge含量的沟道层; 形成在所述基板上的栅极叠层和形成在所述栅极堆叠的两侧上的一个或多个层的侧壁; 金属源和金属漏极分别形成在沟道层中和栅极堆叠的两侧; 以及分别形成在基板和金属源之间以及基板和金属引线之间的绝缘层。

公开(公告)号：US20140145312A1

公开(公告)日：2014-05-29

申请号：US13816173

申请日：2012-12-18

申请人： Jing Wang ,  Renrong Liang ,  Lei Guo ,  Jun Xu

发明人： Jing Wang ,  Renrong Liang ,  Lei Guo ,  Jun Xu

IPC分类号： H01L29/02

CPC分类号： H01L29/02 ,  H01L21/02507 ,  H01L21/0251 ,  H01L21/28255 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/517 ,  H01L29/78

摘要： A semiconductor structure with a rare earth oxide is provided. The semiconductor structure comprises: a semiconductor substrate (100); and a plurality of insulation oxide layers (201, 202 . . . 20x) and a plurality of single crystal semiconductor layers (301, 302 . . . 30x) alternately stacked on the semiconductor substrate (100). A material of the insulation oxide layer (201) contacted with the semiconductor substrate (100) is any one of a rare earth oxide, SiO2, SiOxNy and a combination thereof, a material of other insulation oxide layers (202 . . . 20x) is a single crystal rare earth oxide.

摘要翻译： 提供了具有稀土氧化物的半导体结构。 半导体结构包括：半导体衬底（100）; 以及交替层叠在半导体基板（100）上的多个绝缘氧化物层（201,202,20.0x）和多个单晶半导体层（301,302,30 ...）。 与半导体衬底（100）接触的绝缘氧化物层（201）的材料是稀土氧化物，SiO 2，SiO x N y及其组合中的任一种，其它绝缘氧化物层（202.0×20×）的材料为 单晶稀土氧化物。

公开(公告)号：US20130295733A1

公开(公告)日：2013-11-07

申请号：US13935850

申请日：2013-07-05

申请人： Jing Wang ,  Jun Xu ,  Lei Guo

发明人： Jing Wang ,  Jun Xu ,  Lei Guo

IPC分类号： H01L29/66

CPC分类号： H01L29/665 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/778 ,  H01L29/7833

摘要： A Si—Ge—Si semiconductor structure having double compositionally-graded hetero-structures is provided, comprising: a substrate; a buffer layer or an insulation layer formed on the substrate; a strained SiGe layer formed on the buffer layer or the insulation layer, wherein a Ge content in a central portion of the strained SiGe layer is higher than the Ge content in an upper surface or in a lower surface of the strained SiGe layer, and the Ge content presents a compositionally-graded distribution from the central portion to the upper surface and to the lower surface respectively. According to the present disclosure, a compositionally-graded hetero-structure replaces an abrupt hetero-structure so as to form a triangular hole carrier potential well, so that most of hole carriers may be distributed in the strained SiGe layer with high Ge content and a reduction of the carrier mobility caused by interface scattering may be avoided, thus further improving a performance of a device.

摘要翻译： 提供了具有双组分梯度异质结构的Si-Ge-Si半导体结构，包括：基板; 形成在基板上的缓冲层或绝缘层; 形成在缓冲层或绝缘层上的应变SiGe层，其中应变SiGe层的中心部分的Ge含量高于应变SiGe层的上表面或下表面中的Ge含量， Ge含量呈现出从中心部分到上表面和下表面的成分分级分布。 根据本公开，组成渐变异质结构取代了突变异质结构以便形成三角形空穴载流子阱，使得大多数空穴载流子可以分布在具有高Ge含量的应变SiGe层中，并且 可以避免由界面散射引起的载流子迁移率的降低，从而进一步提高器件的性能。

公开(公告)号：US08455858B2

公开(公告)日：2013-06-04

申请号：US13120122

申请日：2010-11-08

申请人： Jing Wang ,  Jun Xu ,  Lei Guo

发明人： Jing Wang ,  Jun Xu ,  Lei Guo

IPC分类号： H01L29/06 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L29/7391 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/7833 ,  H01L29/785

摘要： A semiconductor structure is provided. The semiconductor structure may include a substrate (100); a buffer layer or an insulation layer (200) formed on the substrate; a first strained wide bandgap semiconductor material layer (400) formed on the buffer layer or the insulation layer; a strained narrow bandgap semiconductor material layer (500) formed on the first strained wide bandgap semiconductor material layer; a second strained wide bandgap semiconductor material layer (700) formed on the strained narrow bandgap semiconductor material layer; a gate stack (300) formed on the second strained wide bandgap semiconductor material layer; and a source and a drain (600) formed in the first strained wide bandgap semiconductor material layer, the strained narrow bandgap semiconductor material layer and the second strained wide bandgap semiconductor material layer respectively.

摘要翻译： 提供半导体结构。 半导体结构可以包括衬底（100）; 形成在所述基板上的缓冲层或绝缘层（200）; 形成在缓冲层或绝缘层上的第一应变宽带隙半导体材料层（400） 形成在第一应变宽带隙半导体材料层上的应变窄带隙半导体材料层（500） 形成在应变窄带隙半导体材料层上的第二应变宽带隙半导体材料层（700） 形成在第二应变宽带隙半导体材料层上的栅叠层（300） 以及形成在第一应变宽带隙半导体材料层中的源极和漏极（600），应变窄带隙半导体材料层和第二应变宽带隙半导体材料层。

公开(公告)号：US20120228707A1

公开(公告)日：2012-09-13

申请号：US13263222

申请日：2011-08-25

申请人： Jing Wang ,  Jun Xu ,  Lei Guo

发明人： Jing Wang ,  Jun Xu ,  Lei Guo

IPC分类号： H01L27/12 ,  H01L21/336

CPC分类号： H01L29/78684 ,  H01L29/7846

摘要： A strained Ge-on-insulator structure is provided, comprising: a silicon substrate, in which an oxide insulating layer is formed on a surface of the silicon substrate; a Ge layer formed on the oxide insulating layer, in which a first passivation layer is formed between the Ge layer and the oxide insulating layer; a gate stack formed on the Ge layer, a channel region formed below the gate stack, and a source and a drain formed on sides of the channel region; and a plurality of shallow trench isolation structures extending into the silicon substrate and filled with an insulating dielectric material to produce a strain in the channel region. Further, a method for forming the strained Ge-on-insulator structure is also provided.

摘要翻译： 提供了一种应变绝缘体上的结构，包括：硅衬底，其中在硅衬底的表面上形成氧化物绝缘层; 形成在所述氧化物绝缘层上的Ge层，其中在所述Ge层和所述氧化物绝缘层之间形成第一钝化层; 形成在Ge层上的栅极叠层，形成在栅叠层下方的沟道区，以及形成在沟道区的侧面上的源极和漏极; 以及延伸到硅衬底中并填充有绝缘电介质材料以在沟道区域中产生应变的多个浅沟槽隔离结构。 此外，还提供了用于形成应变的绝缘体上Ge的结构的方法。

公开(公告)号：US20120187487A1

公开(公告)日：2012-07-26

申请号：US13201903

申请日：2011-07-07

申请人： Jing Wang ,  Jun Xu ,  Lei Guo

发明人： Jing Wang ,  Jun Xu ,  Lei Guo

IPC分类号： H01L27/12 ,  H01L21/336

CPC分类号： H01L29/78684 ,  H01L21/28255 ,  H01L21/76256 ,  H01L29/66742 ,  H01L29/78603

摘要： A method for forming a Ge-on-insulator structure is provided, comprising steps of: forming a Ge layer (1200) on a substrate (2000); treating a first surface of the Ge layer (1200) to form a first semiconducting metal-germanide passivation layer (1300); bonding the first semiconducting metal-germanide passivation layer (1300) with a silicon substrate (1100), wherein on a surface of the silicon substrate (1100) an oxide insulating layer is formed; and removing the substrate (2000). Further, a Ge-on-insulator structure formed by the method is also provided.

摘要翻译： 提供一种形成绝缘体上Ge结构的方法，包括以下步骤：在衬底（2000）上形成Ge层（1200）; 处理所述Ge层（1200）的第一表面以形成第一半导体金属 - 锗化物钝化层（1300）; 将第一半导体金属 - 锗化物钝化层（1300）与硅衬底（1100）接合，其中在所述硅衬底（1100）的表面上形成氧化物绝缘层; 并移除基板（2000）。 此外，还提供了通过该方法形成的绝缘体上Ge结构。