利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

35 条记录 (耗时 0.016 秒)

    Integrated capacitor with a high breakdown voltage
    1.
    发明申请
    Integrated capacitor with a high breakdown voltage 审中-公开
    具有高击穿电压的集成电容器

    公开(公告)号：US20070096253A1

    公开(公告)日：2007-05-03

    申请号：US11436117

    申请日：2006-05-17

    申请人： Joaquin Torres ,  Alexis Farcy

    发明人： Joaquin Torres ,  Alexis Farcy

    IPC分类号： H01L29/00

    CPC分类号： H01L28/91 ,  H01L27/0805 ,  H01L28/65

    摘要： A capacitor incorporated into an integrated electronic circuit comprises two plates and a series of intermediate layers placed between the plates. The intermediate layers are alternately insulating layers and conducting layers, and each conducting layer is electrically isolated from the rest of the circuit. Such a capacitor may have a high breakdown voltage.

    摘要翻译： 并入集成电子电路中的电容器包括两个板和放置在板之间的一系列中间层。 中间层是交替绝缘层和导电层，并且每个导电层与电路的其余部分电隔离。 这种电容器可能具有高击穿电压。

    Integrated circuit comprising an auxiliary component, for example a passive component or a microelectromechanical system, placed above an electronic chip, and the corresponding fabrication process
    2.
    发明授权
    Integrated circuit comprising an auxiliary component, for example a passive component or a microelectromechanical system, placed above an electronic chip, and the corresponding fabrication process 有权
    包括放置在电子芯片上方的辅助部件，例如无源部件或微机电系统的集成电路，以及相应的制造工艺

    公开(公告)号：US06846690B2

    公开(公告)日：2005-01-25

    申请号：US10308482

    申请日：2002-12-03

    申请人： Alexis Farcy ,  Philippe Coronel ,  Pascal Ancey ,  Joaquin Torres

    发明人： Alexis Farcy ,  Philippe Coronel ,  Pascal Ancey ,  Joaquin Torres

    IPC分类号： B81B7/00 ,  B81C3/00 ,  H01L21/00 ,  H01L21/30

    CPC分类号： B81C1/0023 ,  B29C2043/5825

    摘要： The fabrication of an integrated circuit includes a first phase of producing an electronic chip and a second phase of producing at least one auxiliary component placed above the chip and of producing a protective cover which covers the auxiliary component. The first phase of producing the chip is effected from a first semiconductor substrate and comprises the formation of a cavity lying in a chosen region of the chip and emerging at the upper surface of the chip. The second production phase includes the production of the auxiliary component from a second semiconductor substrate, separate from the first, and then the placement in the cavity of the auxiliary component supported by the second substrate and the mutual adhesion of the second substrate to the upper surface of the chip lying outside the cavity. The second substrate then also forms the protective cover.

    摘要翻译： 集成电路的制造包括制造电子芯片的第一阶段和产生放置在芯片上方的至少一个辅助部件并产生覆盖辅助部件的保护盖的第二阶段。 制造芯片的第一阶段从第一半导体衬底实现，并且包括形成位于芯片的选定区域中并且出现在芯片的上表面处的空腔。 第二生产阶段包括从第二半导体衬底生产辅助部件，与第一半导体衬底分离，然后放置在由第二衬底支撑的辅助部件的空腔中，以及将第二衬底与上表面的相互粘合 的芯片位于腔外。 第二基板然后也形成保护盖。

    Integrated electronic circuit incorporating a capacitor
    4.
    发明申请
    Integrated electronic circuit incorporating a capacitor 审中-公开
    集成电子电路

    公开(公告)号：US20070063240A1

    公开(公告)日：2007-03-22

    申请号：US11518539

    申请日：2006-09-07

    申请人： Joaquin Torres ,  Alexis Farcy

    发明人： Joaquin Torres ,  Alexis Farcy

    IPC分类号： H01L29/94

    CPC分类号： H01L27/0688 ,  H01L28/60 ,  H01L28/75

    摘要： An integrated electronic circuit includes electrical connections located in metallization layers superposed on top of a substrate. The circuit further incorporates a capacitor having two plates that are placed in two adjacent metallization layers. Each of the metallization layers containing a capacitor plate further contains electrical connections. The capacitor is compatible with a high level of integration of the circuit and may be produced using the damascene process.

    摘要翻译： 集成电子电路包括位于叠加在基板顶部上的金属化层中的电连接。 电路还包括具有放置在两个相邻的金属化层中的两个板的电容器。 包含电容器板的每个金属化层还包含电连接。 电容器与电路的高集成度兼容，并且可以使用镶嵌工艺制造。

    Control of carbon nanostructure growth in an interconnect structure
    6.
    发明授权
    Control of carbon nanostructure growth in an interconnect structure 有权
    控制互连结构中的碳纳米结构生长

    公开(公告)号：US08399772B2

    公开(公告)日：2013-03-19

    申请号：US12439919

    申请日：2007-08-29

    申请人： Laurent Gosset ,  Joaquin Torres

    发明人： Laurent Gosset ,  Joaquin Torres

    IPC分类号： H05K1/00 ,  H05K1/11 ,  H05K1/16

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L21/76831 ,  H01L21/76879 ,  H01L29/0673 ,  H01L29/0676 ,  H01L2221/1094

    摘要： An interconnect structure on a substrate is provided. The interconnect structure comprises electrically conductive interconnect elements on at least two interconnect levels on or above a substrate level. In the interconnect structure of the invention, at least one electrically conductive via connects a first interconnect element on one interconnect level or on the substrate level to a second interconnect element on a different interconnect level. The via extends in a via opening of a first dielectric layer and comprises an electrically conductive via material that contains electrically conductive cylindrical carbon nanostructures. At least one cover-layer segment reaches into a lateral extension of the via opening and defines a via aperture that is small enough to prevent a penetration of the carbon nanostructures through the via aperture. This structure enhances control of carbon nanostructure growth in a height direction during fabrication of the interconnect structure.

    摘要翻译： 提供了衬底上的互连结构。 互连结构包括在衬底层上或上方的至少两个互连层上的导电互连元件。 在本发明的互连结构中，至少一个导电通孔将一个互连层上的第一互连元件或基板层上的第一互连元件连接到不同互连层上的第二互连元件。 通孔在第一电介质层的通孔中延伸，并且包括含有导电圆柱形碳纳米结构的导电通孔材料。 至少一个覆盖层段到达通孔开口的横向延伸部分，并限定通孔孔，其足够小以防止碳纳米结构穿过通孔。 该结构在互连结构的制造期间增强了在高度方向上碳纳米结构生长的控制。

    CuSiN/SiN diffusion barrier for copper in integrated-circuit devices
    7.
    发明授权
    CuSiN/SiN diffusion barrier for copper in integrated-circuit devices 有权
    集成电路器件中铜的CuSiN / SiN扩散阻挡层

    公开(公告)号：US08072075B2

    公开(公告)日：2011-12-06

    申请号：US12439910

    申请日：2007-08-29

    申请人： Nicolas Jourdan ,  Laurant Georges Gosset ,  Joaquin Torres

    发明人： Nicolas Jourdan ,  Laurant Georges Gosset ,  Joaquin Torres

    IPC分类号： H01L23/48 ,  H01L21/4763

    CPC分类号： H01L21/76831 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76855 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention relates to an integrated-circuit device that has at least one Copper-containing feature in a dielectric layer, and a diffusion-barrier layer stack arranged between the feature and the dielectric layer. The integrated-circuit device of the invention has a diffusion-barrier layer stack, which comprises, in a direction from the Copper-containing feature to the dielectric layer, a CuSiN layer and a SiN layer. This layer combination provides an efficient barrier for suppressing Copper diffusion from the feature into the dielectric layer. Furthermore, a CuSiN/SiN layer sequence provides an improved adhesion between the layers of the diffusion-barrier layer stack and the dielectric layer, and thus improves the electromigration performance of the integrated-circuit device during operation. Therefore, the reliability of device operation and the lifetime of the integrate-circuit device are improved in comparison with prior-art devices. The invention further relates to a method for fabricating such an integrated-circuit device.

    摘要翻译： 本发明涉及一种在电介质层中具有至少一个含铜特征的集成电路器件，以及布置在特征和电介质层之间的扩散阻挡层堆叠。 本发明的集成电路器件具有扩散阻挡层堆叠，其包括在从含铜特征到电介质层的方向上具有CuSiN层和SiN层。 该层组合提供了用于抑制从特征进入电介质层的铜扩散的有效屏障。 此外，CuSiN / SiN层序列提供了扩散阻挡层堆叠层和电介质层之间的改进的粘合性，从而提高了集成电路器件在操作期间的电迁移性能。 因此，与现有技术的装置相比，提高了器件工作的可靠性和集成电路器件的寿命。 本发明还涉及一种用于制造这种集成电路器件的方法。

    Formation of a reliable diffusion-barrier cap on a Cu-containing interconnect element having grains with different crystal orientations
    8.
    发明授权
    Formation of a reliable diffusion-barrier cap on a Cu-containing interconnect element having grains with different crystal orientations 有权
    在具有不同晶体取向的晶粒的含Cu互连元件上形成可靠的扩散阻挡帽

    公开(公告)号：US07989342B2

    公开(公告)日：2011-08-02

    申请号：US12529647

    申请日：2008-03-03

    申请人： Joaquin Torres ,  Laurent Gosset ,  Sonarith Chhun ,  Vincent Arnal

    发明人： Joaquin Torres ,  Laurent Gosset ,  Sonarith Chhun ,  Vincent Arnal

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76849 ,  H01L21/76834 ,  H01L21/76867 ,  H01L21/76889

    摘要： The present invention relates to a method for fabricating a diffusion-barrier cap on a Cu-containing interconnect element that has crystallites of at least two different crystal orientations, comprises selectively incorporating Si into only a first set of crystallites with at least one first crystal orientation, employing first process conditions, and subsequently selectively forming a first adhesion-layer portion comprising CuSi and a first diffusion-barrier-layer portion only on the first set of crystallites, thus forming a first barrier-cap portion, and subsequently selectively incorporating Si into only the second set of crystallites, employing second process conditions that differ from the first process conditions, and forming a second barrier-cap portion comprising a Si-containing second diffusion-barrier layer portion on the second set of crystallites of the interconnect element. The processing improves the properties of the diffusion-barrier cap and secures a continuous formation of a diffusion-barrier layer on the interconnect element.

    摘要翻译： 本发明涉及一种在具有至少两种不同晶体取向的微晶的含Cu互连元件上制造扩散阻挡帽的方法，包括选择性地将Si掺入到仅具有至少一个第一晶体取向的第一组微晶中 采用第一工艺条件，随后在第一组微晶上选择性地形成包含CuSi和第一扩散阻挡层部分的第一粘附层部分，从而形成第一阻挡帽部分，随后选择性地将Si并入 仅使用第二组微晶，采用与第一工艺条件不同的第二工艺条件，以及在互连元件的第二组微晶上形成包含含Si的第二扩散阻挡层部分的第二阻挡帽部分。 该处理改善了扩散阻挡帽的性质，并确保了互连元件上的扩散阻挡层的连续形成。

    Copper diffusion barrier
    9.
    发明授权
    Copper diffusion barrier 有权
    铜扩散屏障

    公开(公告)号：US08729701B2

    公开(公告)日：2014-05-20

    申请号：US12882577

    申请日：2010-09-15

    申请人： Nicolas Jourdan ,  Joaquin Torres

    发明人： Nicolas Jourdan ,  Joaquin Torres

    IPC分类号： H01L23/532

    CPC分类号： H01L21/76843 ,  H01L21/76831 ,  H01L21/76864 ,  H01L21/76868 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The invention concerns a method of forming a copper portion surrounded by an insulating material in an integrated circuit structure, the insulating material being a first oxide, the method having steps including forming a composite material over a region of the insulating material where the copper portion is to be formed, the composite material having first and second materials, annealing such that the second material reacts with the insulating material to form a second oxide that provides a diffusion barrier to copper; and depositing a copper layer over the composite material by electrochemical deposition to form the copper portion.

    摘要翻译： 本发明涉及一种形成由集成电路结构中的绝缘材料包围的铜部分的方法，绝缘材料是第一氧化物，该方法包括在绝缘材料的区域上形成复合材料，其中铜部分为 要形成的具有第一和第二材料的复合材料退火，使得第二材料与绝缘材料反应以形成向铜提供扩散阻挡层的第二氧化物; 以及通过电化学沉积在复合材料上沉积铜层以形成铜部分。

    Controlling lateral distribution of air gaps in interconnects
    10.
    发明授权
    Controlling lateral distribution of air gaps in interconnects 有权
    控制互连中气隙的横向分布

    公开(公告)号：US08110879B2

    公开(公告)日：2012-02-07

    申请号：US12581370

    申请日：2009-10-19

    申请人： Joaquin Torres ,  Laurent-Georges Gosset

    发明人： Joaquin Torres ,  Laurent-Georges Gosset

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L21/7682

    摘要： Properties of a hard mask liner are used against the diffusion of a removal agent to prevent air cavity formation in specific areas of an interconnect stack. According to one embodiment, there is provided a method in which there is defined a portion on a surface of an IC interconnect stack as being specific to air cavity introduction, with the defined portion being smaller than the surface of the substrate. At least one metal track is produced within the interconnect stack, and there is deposited at least one interconnect layer having a sacrificial material and a permeable material within the interconnect stack. There is defined at least one trench area surrounding the defined portion and forming at least one trench, and a hard mask layer is deposited to coat the trench. At least one air cavity is formed below the defined portion of the surface by using a removal agent for removing the sacrificial material to which the permanent material is resistant.

    摘要翻译： 使用硬掩模衬垫的性质来抵抗除去剂的扩散，以防止在互连叠层的特定区域中形成空腔。 根据一个实施例，提供了一种方法，其中在IC互连叠层的表面上限定了特定于空气腔引入的部分，其中限定部分小于衬底的表面。 在互连堆叠内产生至少一个金属轨道，并且在互连叠层内沉积至少一个具有牺牲材料和可渗透材料的互连层。 限定围绕限定部分的至少一个沟槽区域并形成至少一个沟槽，并且沉积硬掩模层以涂覆沟槽。 通过使用用于除去永久材料所抵抗的牺牲材料的去除剂，在表面的限定部分下方形成至少一个空气腔。