公开(公告)号：US6028015A

公开(公告)日：2000-02-22

申请号：US281514

申请日：1999-03-29

申请人： Zhihai Wang ,  Wilbur G. Catabay ,  Joe W. Zhao

发明人： Zhihai Wang ,  Wilbur G. Catabay ,  Joe W. Zhao

IPC分类号： H01L21/3105 ,  H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L21/469

CPC分类号： H01L21/76826 ,  H01L21/3105 ,  H01L21/3122 ,  H01L21/76814 ,  H01L21/76831

摘要： A process is described for treating damaged surfaces of a low dielectric constant organo silicon oxide insulation layer of an integrated circuit structure to inhibit absorption of moisture which comprises treating such damaged surfaces of said organo silicon oxide insulation layer with a hydrogen plasma. The treatment with hydrogen plasma causes hydrogen to bond to silicon atoms with dangling bonds in the damaged surface of the organo silicon oxide layer to replace organic material severed from such silicon atoms at the damaged surface, whereby absorption of moisture in the damaged surface of the organo silicon oxide layer, by bonding of such silicon dangling bonds with moisture, is inhibited.

摘要翻译： 描述了一种处理集成电路结构的低介电常数有机氧化硅绝缘层的损伤表面以抑制水分吸收的方法，其包括用氢等离子体处理所述有机氧化硅绝缘层的这种损坏表面。 用氢等离子体处理可以使有机硅氧化物层受损表面的氢键键合到具有悬挂键的硅原子上，以取代被损坏的表面从这种硅原子上切下的有机材料，从而吸收有机物损坏表面的水分 通过这种硅悬挂键与水分的结合，氧化硅层被抑制。

公开(公告)号：US5660682A

公开(公告)日：1997-08-26

申请号：US615437

申请日：1996-03-14

申请人： Joe W. Zhao ,  Zhihai Wang ,  Wilbur G. Catabay

发明人： Joe W. Zhao ,  Zhihai Wang ,  Wilbur G. Catabay

IPC分类号： H01L21/302 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/768 ,  H01L21/461

CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/76814

摘要： A method of removing material from an integrated circuit. The integrated circuit is placed within a reaction chamber, and a flow of argon and a flow of hydrogen are introduced into the reaction chamber, where the flow of hydrogen is greater than the flow of argon. The flows of argon and hydrogen are energized to form a plasma, and the material is removed from the integrated circuit by reaction of the material with the energized flows of argon and hydrogen to form gaseous products, which are pumped out of the reaction chamber. The plasma and flows of argon and hydrogen are discontinued when a desired amount of material has been removed, and the integrated circuit is removed from the reaction chamber.

摘要翻译： 从集成电路中去除材料的方法。 将集成电路放置在反应室内，并且将氩气和氢气流引入反应室中，其中氢气流量大于氩气流量。 氩气和氢气的流动被激发以形成等离子体，并且通过材料与激励的氩气和氢气流的反应将材料从集成电路移除，以形成气态产物，其被泵出反应室。 当去除所需量的材料时，停止等离子体和氩气和氢气的流动，并且将集成电路从反应室中取出。

公开(公告)号：US06368979B1

公开(公告)日：2002-04-09

申请号：US09607511

申请日：2000-06-28

申请人： Zhihai Wang ,  Wilbur G. Catabay ,  Joe W. Zhao

发明人： Zhihai Wang ,  Wilbur G. Catabay ,  Joe W. Zhao

IPC分类号： H01L2100

CPC分类号： H01L21/7681 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76813

摘要： A dual damascene type of structure of vias and trenches formed using layers of low k dielectric material is disclosed, and a process for making same without damage to the low k dielectric material during removal of photoresist masks used respectively in the formation of the pattern of via openings and the pattern of trench openings in the layers of low k dielectric material. Damage to the low k dielectric material is avoided by forming a first layer of low k dielectric material on an integrated circuit structure; forming a first hard mask layer over the first layer of low k dielectric material; forming over the first hard mask layer a first photoresist mask having a pattern of via openings therein; and then etching the first hard mask layer through the first photoresist mask to form a first hard mask having the pattern of vias openings replicated therein, using an etch system which will also remove the first photoresist mask. The first photoresist mask (the via mask) is, therefore, removed during the formation of the first hard mask, instead of in a separate oxidizing step which would damage the low k dielectric material. Damage to the low k dielectric material during removal of the second photoresist mask (the trench mask) is also avoided by depositing a second layer of low k dielectric material over the first hard mask; forming over the second layer of low k dielectric material a second hard mask layer; forming over the second hard mask layer a second photoresist mask having a pattern of trench openings therein; and then forming the second hard mask by etching the second hard mask layer through the second photoresist resist mask to form a second hard mask having the pattern of trench openings replicated therein, using at etch system which will also remove the second photoresist mask. Thus, the second photoresist mask (the trench mask) is also removed during the formation of the second hard mask, instead of in a separate oxidizing step which would damage the low k dielectric material.

公开(公告)号：US5770520A

公开(公告)日：1998-06-23

申请号：US760466

申请日：1996-12-05

申请人： Joe W. Zhao ,  Zhihai Wang ,  Wilbur G. Catabay

发明人： Joe W. Zhao ,  Zhihai Wang ,  Wilbur G. Catabay

IPC分类号： C23C16/42 ,  C23C16/34 ,  H01L21/285 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76843 ,  C23C16/34

摘要： Described is a barrier layer in an integrated circuit structure which is formed in a via or contact opening over an underlying material in which diffusion of the underlying material (or filler material deposited over the barrier layer) through the barrier layer is inhibited without unduly increasing the thickness and resistivity of the barrier layer. This is accomplished by substituting an amorphous material for the crystalline titanium nitride to thereby eliminate the present of grain boundaries which are believed to provide the diffusion path through the titanium nitride material. In a preferred embodiment, the amorphous barrier layer comprises an amorphous ternary Ti--Si--N material formed using a source of titanium, a source of silicon, and a source of nitrogen. None of the source materials should contain oxygen to avoid formation of undesirable oxides which would increase the resistivity of the barrier layer. In a particularly preferred embodiment, an organic source of titanium is used, and either or both of the silicon and nitrogen sources are capable of reacting with the organic portion of the organic titanium reactant to form gaseous byproducts which can then be removed from the deposition chamber to inhibit the formation of carbon deposits in the chamber or on the integrated circuit structure.

摘要翻译： 描述了集成电路结构中的阻挡层，其形成在下面的材料中的通孔或接触开口中，其中下面的材料（或沉积在阻挡层上的填充材料）通过阻挡层的扩散被抑制，而不会不适当地增加 阻挡层的厚度和电阻率。 这通过用无定形材料代替结晶氮化钛来实现，从而消除据信提供通过氮化钛材料的扩散路径的晶界的存在。 在优选实施例中，非晶形阻挡层包括使用钛源，硅源和氮源形成的无定形三元Ti-Si-N材料。 源材料都不应含有氧，以避免形成不希望的氧化物，这会增加阻挡层的电阻率。 在一个特别优选的实施方案中，使用有机钛源，并且硅和氮源中的任一种或两者能够与有机钛反应物的有机部分反应以形成气态副产物，然后可以从沉积室 以抑制室内或集成电路结构上的碳沉积物的形成。

公开(公告)号：US07229923B2

公开(公告)日：2007-06-12

申请号：US10772133

申请日：2004-02-03

申请人： Wilbur G. Catabay ,  Zhihai Wang ,  Ping Li

发明人： Wilbur G. Catabay ,  Zhihai Wang ,  Ping Li

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76859 ,  H01L21/76864 ,  H01L21/76871 ,  H01L21/76873 ,  H01L21/76874 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods for forming robust copper structures include steps for providing a substrate with an insulating layer with openings formed therein. At least two barrier layers are then formed followed by the deposition of a copper seed layer which is annealed. Bulk copper deposition of copper and planarization can follow. In one approach the seed layer is implanted with suitable materials forming an implanted seed layer upon which a bulk layer of conductive material is formed and annealed to form a final barrier layer. In another approach, a barrier layer is formed between two seed layers which forms a base for bulk copper deposition. Another method involves forming a first barrier layer and forming a copper seed layer thereon. The seed layer being implanted with a barrier material (e.g. palladium, chromium, tantalum, magnesium, and molybdenum or other suitable materials) and then bulk deposition of copper-containing material is performed followed by annealing.

摘要翻译： 用于形成坚固的铜结构的方法包括为衬底提供其中形成有开口的绝缘层的步骤。 然后形成至少两个阻挡层，随后沉积退火的铜籽晶层。 大量铜沉积铜和平坦化可以遵循。 在一种方法中，用形成植入种子层的合适材料注入种子层，在其上形成导电材料的主体层并退火以形成最终的阻挡层。 在另一种方法中，在形成用于大量铜沉积的基底的两个种子层之间形成阻挡层。 另一种方法包括形成第一阻挡层并在其上形成铜籽晶层。 植入具有阻挡材料（例如钯，铬，钽，镁和钼或其它合适材料）的籽晶层，然后进行含铜材料的堆积沉积，然后进行退火。

公开(公告)号：US07413984B2

公开(公告)日：2008-08-19

申请号：US11733673

申请日：2007-04-10

申请人： Wilbur G. Catabay ,  Zhihai Wang ,  Ping Li

发明人： Wilbur G. Catabay ,  Zhihai Wang ,  Ping Li

IPC分类号： H01L21/44

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76858 ,  H01L21/76859 ,  H01L21/76864 ,  H01L21/76871 ,  H01L21/76873 ,  H01L21/76874 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the invention include a method for forming a copper interconnect having a bi-layer copper barrier layer. The method comprises the steps of providing a substrate with a low-K dielectric insulating layer and an opening in the insulating layer. A first barrier layer of tantalum/tantalum nitride is formed on the insulating layer and in the opening. A second barrier layer consisting of a material selected from the group of palladium, chromium, tantalum, magnesium, and molybdenum is formed on the first barrier layer. A copper seed layer is formed on the second barrier layer and implanted with barrier ions and a bulk copper layer is formed on the seed layer. The substrate is annealed and subject to further processing which can include planarization.

摘要翻译： 本发明的实施例包括一种形成具有双层铜阻挡层的铜互连的方法。 该方法包括以下步骤：在绝缘层中提供具有低K电介质绝缘层和开口的衬底。 在绝缘层和开口中形成钽/氮化钽的第一阻挡层。 在第一阻挡层上形成由选自钯，铬，钽，镁和钼的材料构成的第二阻挡层。 在第二阻挡层上形成铜籽晶层，并注入势垒离子，并在籽晶层上形成体铜层。 将衬底退火并进行可包括平坦化的进一步加工。

公开(公告)号：US07259462B1

公开(公告)日：2007-08-21

申请号：US11419548

申请日：2006-05-22

申请人： Wai Lo ,  Hong Lin ,  Shiqun Gu ,  Wilbur G. Catabay ,  Zhihai Wang ,  Wei-Jen Hsia

发明人： Wai Lo ,  Hong Lin ,  Shiqun Gu ,  Wilbur G. Catabay ,  Zhihai Wang ,  Wei-Jen Hsia

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/7682 ,  H01L21/76838 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.

摘要翻译： 对形成集成电路的方法的改进。 形成蚀刻停止层以覆盖集成电路的前端处理层。 形成支撑结构，其被布置为支撑集成电路的各个级别上的导电互连。 基本上去除了在制造互连期间形成的蚀刻停止层上方的所有非导电层。

公开(公告)号：US06472314B1

公开(公告)日：2002-10-29

申请号：US09968944

申请日：2001-10-02

申请人： Wilbur G. Catabay ,  Zhihai Wang

发明人： Wilbur G. Catabay ,  Zhihai Wang

IPC分类号： H01L21768

CPC分类号： H01L21/76846

摘要： A method of forming an electrically conductive interconnect on a substrate. An interconnection feature is formed on the substrate, and a first barrier layer is deposited on the substrate. The first barrier layer consists essentially of a diamond film. A seed layer consisting essentially of copper is deposited on the substrate, and a conductive layer consisting essentially of copper is deposited on the substrate. Thus, by using a diamond film as the barrier layer, diffusion of the copper from the conductive layer into the material of the substrate is substantially reduced and preferably eliminated.

摘要翻译： 一种在衬底上形成导电互连的方法。 在衬底上形成互连特征，并且在衬底上沉积第一阻挡层。 第一阻挡层基本上由金刚石膜组成。 基本上由铜组成的晶种层沉积在基片上，并且基本上由铜组成的导电层沉积在基片上。 因此，通过使用金刚石膜作为阻挡层，铜从导电层扩散到基板的材料中显着地减少并且优选地被消除。

公开(公告)号：US07081406B2

公开(公告)日：2006-07-25

申请号：US10915719

申请日：2004-08-10

申请人： Wai Lo ,  Hong Lin ,  Shiqun Gu ,  Wilbur G. Catabay ,  Zhihai Wang ,  Wei-Jen Hsia

发明人： Wai Lo ,  Hong Lin ,  Shiqun Gu ,  Wilbur G. Catabay ,  Zhihai Wang ,  Wei-Jen Hsia

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/76838 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.

摘要翻译： 对形成集成电路的方法的改进。 形成蚀刻停止层以覆盖集成电路的前端处理层。 形成支撑结构，其被布置为支撑集成电路的各个级别上的导电互连。 基本上去除了在制造互连期间形成的蚀刻停止层上方的所有非导电层。

公开(公告)号：US06881664B2

公开(公告)日：2005-04-19

申请号：US10614776

申请日：2003-07-07

申请人： Wilbur G. Catabay ,  Richard Schinella ,  Zhihai Wang ,  Wei-Jen Hsia

发明人： Wilbur G. Catabay ,  Richard Schinella ,  Zhihai Wang ,  Wei-Jen Hsia

IPC分类号： B23H5/08 ,  C23F4/00 ,  C25F3/02 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/44

CPC分类号： H01L21/7684 ,  B23H5/08 ,  C23F4/00 ,  C25F3/02 ,  H01L21/32115 ,  H01L21/3212 ,  H01L21/32136

摘要： A three step process for planarizing an integrated circuit structure comprising one or more dielectric layers having trench and/or via openings therein lined with a layer of electrically conductive barrier liner material and filled with copper filler material.Sufficient excess copper (formed over the barrier liner portions on the top surface of the dielectric layer) is removed in an initial chemical mechanical polish (CMP) step to provide a planarized copper layer with a global planarity of about 20 nm to about 30 nm. The remainder of the excess copper over the portion of the barrier liner material lying on the top surface of the dielectric layer is then removed by electropolishing the structure, in a second step, until all of the excess copper over the portion of the barrier liner material lying on the top surface of the dielectric layer is removed. In a third step, all remaining portions of the diffusion barrier liner on the upper surface of the low k dielectric layer are then removed using a dry etching process selective to copper and the dielectric layer until all of the portions of the barrier layer over the top surface of the dielectric layer are removed; whereby the integrated circuit structure may be planarized by removal of all of the copper layer and barrier layer from the top surface of the dielectric layer while inhibiting dishing and/or erosion of the surface of copper filler material in the opening, and without risking distortion and/or delamination by the harsh effects of excessive CMP processing.

摘要翻译： 一种用于平面化集成电路结构的三步法，该集成电路结构包括其中具有沟槽和/或通孔开口的一个或多个电介质层，内衬有一层导电阻挡衬里材料并填充有铜填充材料。 在初始化学机械抛光（CMP）步骤中除去足够的过量铜（形成在电介质层的顶表面上的阻挡衬里部分上），以提供具有约20nm至约30nm的全局平面度的平坦化的铜层。 然后通过在第二步骤中电解抛光该结构，直到在阻挡衬里材料的部分上的所有过量的铜之前，将位于介电层顶表面上的阻挡衬里材料部分上的剩余的铜剩余部分除去 位于介电层的顶表面上被去除。 在第三步骤中，然后使用对铜和电介质层有选择性的干式蚀刻工艺去除低k电介质层的上表面上的扩散阻挡衬垫的所有剩余部分，直到阻挡层的所有部分超过顶部 去除电介质层的表面; 从而通过从电介质层的顶表面去除所有的铜层和阻挡层，同时抑制开口中铜填充材料的表面的凹陷和/或侵蚀，并且不会产生变形和风险，从而平面化集成电路结构 /或由于过度的CMP加工造成的恶劣影响而分层。