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公开(公告)号：US5031029A
公开(公告)日：1991-07-09
申请号：US504496
申请日：1990-04-04
申请人： John Acocella , Nanik Bakhru , Alfred Grill , Egidio Marotta , Bernard S. Meyerson , Vishnubhai V. Patel
发明人： John Acocella , Nanik Bakhru , Alfred Grill , Egidio Marotta , Bernard S. Meyerson , Vishnubhai V. Patel
IPC分类号： H01L23/373
CPC分类号： H01L23/3735 , H01L2224/16 , H01L2224/73253 , H01L2924/01014 , H01L2924/04941 , Y10S165/905
摘要： A device that contains a copper substrate; a rigidizing layer and/or a metal layer, and a non-graphitic hard carbon layer deposited on the rigidizing layer; and use as a heat sink or piston for electronic components.
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公开(公告)号：US5241131A
公开(公告)日：1993-08-31
申请号：US868371
申请日：1992-04-14
申请人： Nanik Bakhru , Alfred Grill , Gregory S. Hopper , Egidio Marotta , Bernard S. Meyerson , Vishnubhai V. Patel
发明人： Nanik Bakhru , Alfred Grill , Gregory S. Hopper , Egidio Marotta , Bernard S. Meyerson , Vishnubhai V. Patel
IPC分类号： H01L23/36 , H01L23/373 , H01L23/433
CPC分类号： H01L23/4336 , H01L23/4338 , H01L2224/16 , Y10T428/30
摘要： The present invention relates generally to a new erosion/corrosion resistant diaphragm, and more particularly to an erosion/corrosion resistant diaphragm that can be used in an apparatus for cooling integrated circuit chips. An erosion/corrosion resistant coating can be provided on one side of a metallic foil that will be exposed to fluid impingement. And, a similar erosion/corrosion resistant coating can be provided on the opposite side of the metallic foil where the normal thermal cycling of the chip might damage the unprotected metallic foil.
摘要翻译： 本发明一般涉及一种新的耐腐蚀/耐腐蚀隔膜，更具体地涉及一种可用于冷却集成电路芯片的设备中的耐腐蚀/耐腐蚀隔膜。 可以在将暴露于流体冲击的金属箔的一侧上提供耐腐蚀/耐腐蚀涂层。 并且，可以在金属箔的相对侧上提供类似的耐腐蚀/耐腐蚀涂层，其中芯片的正常热循环可能损坏未受保护的金属箔。
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公开(公告)号：US5159508A
公开(公告)日：1992-10-27
申请号：US634671
申请日：1990-12-27
CPC分类号： G11B5/6005 , G11B5/3106 , Y10T29/49041
摘要： A magnetic head slider having a protective coating on the rails thereof, the protective coating comprising a thin adhesion layer and a thin layer of amorphous hydrogenated carbon. The protective coating is deposited on the air bearing surface of the slider after the thin film magnetic heads are lapped to a chosen dimension, but before the pattern of rails is produced on the air bearing surface. The protective coating protects the magnetic head during the rail fabrication process and in usage in a magnetic recording system protects the magnetic head from wear and corrosion damage.
摘要翻译： 一种在其轨道上具有保护涂层的磁头滑块，保护涂层包括薄粘合层和非晶氢化碳薄层。 在将薄膜磁头研磨成选定的尺寸之后，但是在空气轴承表面上产生轨道图案之前，保护涂层沉积在滑块的空气支承表面上。 保护涂层在轨道制造过程中保护磁头，并且在磁记录系统中使用可保护磁头免受磨损和腐蚀的损害。
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公开(公告)号：US4647494A
公开(公告)日：1987-03-03
申请号：US793517
申请日：1985-10-31
CPC分类号： G11B5/72 , Y10S428/90 , Y10T428/24975 , Y10T428/265 , Y10T428/30
摘要： A superior wear-resistant coating is provided for metallic magnetic recording layers, where the improved coating is a hard carbon layer that is strongly bound to the underlying metallic magnetic recording layer by an intermediate layer of silicon. The silicon layer can be very thin, with a minimum thickness of a few atomic layers, and provides strong adhesion between the hard carbon protective layer and the metallic magnetic recording layer. A preferred technique for depositing both the intermediate silicon layer and the hard carbon layer is plasma deposition, since both of these depositions can be performed in the same reactor without breaking vacuum.
摘要翻译： 为金属磁记录层提供了优异的耐磨涂层，其中改进的涂层是通过中间层强烈地结合到下面的金属磁记录层的硬碳层。 硅层可以非常薄，具有几个原子层的最小厚度，并且在硬碳保护层和金属磁记录层之间提供牢固的粘附。 用于沉积中间硅层和硬碳层的优选技术是等离子体沉积，因为这两个沉积物都可以在相同的反应器中进行，而不会破坏真空。
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5.发明授权CVD diamond or diamond-like carbon for chemical-mechanical polish etch stop 失效CVD金刚石或类似钻石的化学机械抛光蚀刻碳
公开(公告)号：US5246884A
公开(公告)日：1993-09-21
申请号：US784280
申请日：1991-10-30
IPC分类号： H01L21/304 , H01L21/306 , H01L21/3105 , H01L21/768
CPC分类号： H01L21/31053 , H01L21/76819
摘要： Metallized semiconductor chips, such as are intended for VLSI, are coated with a first layer of SiO2 followed by a second layer of CVD diamond or DLC as an etch stop. The resulting structure is reproducibly and controllably planarized using a chem-mech slurry and an appropriate polishing pad, enabling subsequent layers to be built up similarly.
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6.发明授权Epitaxial and polycrystalline growth of Si1-x-yGexCy and Si1-yCy alloy layers on Si by UHV-CVD 有权Si1-x-yGexCy和Si1-yCy合金层通过UHV-CVD在Si上的外延和多晶生长公开(公告)号：US07405422B2
公开(公告)日：2008-07-29
申请号：US11618770
申请日：2006-12-30
IPC分类号： H01L29/06
CPC分类号： C23C16/325 , C23C16/32 , C30B25/02 , C30B29/52 , H01L21/02381 , H01L21/02447 , H01L21/0245 , H01L21/02505 , H01L21/02529 , H01L21/02532 , H01L21/02694 , Y10T428/12674
摘要： A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitaxial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon
摘要翻译： 描述了一种用于在热壁，等温UHV-CVD系统中在多个基板上沉积单晶，硅碳和硅锗碳外延膜的方法和装置。 特别地，描述了在350℃至750℃的范围内的多晶片低温生长技术，用于在Si和SiGe膜中外延引入碳，其具有非常突然且明确限定的结，但没有任何相关的氧背景污染。 优选地，这些外延SiC和SiGeC膜是原位掺杂的p型或n型，并且存在低浓度的碳<20 20 -3 -3， 生长的p型或n型掺杂物分布可以承受炉退火至850℃的温度和快速热退火温度至1000℃
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7.发明授权Epitaxial and polycrystalline growth of Si1-X-YGEXCY and Si1-YCY alloy layers on Si by UHV-CVD 失效Si1-X-YGEXCY和Si1-YCY合金层通过特高压CVD在Si上的外延和多晶生长公开(公告)号：US07652288B2
公开(公告)日：2010-01-26
申请号：US12163389
申请日：2008-06-27
IPC分类号： H01L29/00
CPC分类号： C23C16/325 , C23C16/32 , C30B25/02 , C30B29/52 , H01L21/02381 , H01L21/02447 , H01L21/0245 , H01L21/02505 , H01L21/02529 , H01L21/02532 , H01L21/02694 , Y10T428/12674
摘要： A method and apparatus for depositing single crystal, epitaxial films of silicon carbon and silicon germanium carbon on a plurality of substrates in a hot wall, isothermal UHV-CVD system is described. In particular, a multiple wafer low temperature growth technique in the range from 350° C. to 750° C. is described for incorporating carbon epitaxially in Si and SiGe films with very abrupt and well defined junctions, but without any associated oxygen background contamination. Preferably, these epitaxial SiC and SiGeC films are in-situ doped p- or n-type and with the presence of low concentration of carbon
摘要翻译： 描述了一种用于在热壁，等温UHV-CVD系统中在多个基板上沉积单晶，硅碳和硅锗碳外延膜的方法和装置。 特别地，描述了在350℃至750℃的范围内的多晶片低温生长技术，用于在Si和SiGe膜中外延引入碳，其具有非常突然且明确限定的结，但没有任何相关的氧背景污染。 优选地，这些外延SiC和SiGeC膜原位掺杂p型或n型，并且存在低浓度的碳<1020cm-3，生长的p型或n型掺杂剂分布可以承受炉退火 到850℃的温度和快速热退火温度至1000℃
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公开(公告)号：US5273829A
公开(公告)日：1993-12-28
申请号：US774010
申请日：1991-10-08
IPC分类号： G01L9/00 , G03F1/22 , H01L21/027 , H01L21/20 , H01L21/205 , H01L21/306 , G03G5/14
CPC分类号： G03F1/22 , G01L9/0042 , H01L21/30608
摘要： The subject invention provides a silicon membrane material made from silicon that is epitaxially deposited at low temperatures greater than or equal to 500.degree. C. and doped with controlled amounts of boron and germanium. A silicon membrane structure is provided and made by one or more layers of ultra thin epitaxially deposited silicon layers that are precisely controlled in both thickness and composition. At least one of the layers is doped with boron in a concentration range greater than 2.times.10.sup.20 atoms of boron per cubic centimeter of silicon, or with germanium in a concentration range greater than 5.times.10.sup.20 atoms of germanium per cubic centimeter of silicon, or with a combination of boron and germanium in these concentration ranges. A silicon membrane fabrication process is also provided which requires no additional masking film to protect the membrane surface during KOH etching of the bulk silicon substrate.
摘要翻译： 本发明提供了由硅制成的硅膜材料，其在大于或等于500℃的低温下外延沉积，并掺杂受控量的硼和锗。 硅膜结构由一层或多层超薄外延沉积的硅层提供并制成，其在厚度和组成上精确控制。 这些层中的至少一层掺杂了硼，其浓度范围大于每立方厘米硅的2×1020个原子的硼，或者锗浓度范围大于每立方厘米硅的5×1020原子，或者与 硼和锗在这些浓度范围内。 还提供了硅膜制造方法，其不需要额外的掩模膜来在体硅衬底的KOH蚀刻期间保护膜表面。
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公开(公告)号：US5151383A
公开(公告)日：1992-09-29
申请号：US307154
申请日：1989-02-06
CPC分类号： H01L33/18 , C23C16/24 , C23C16/46 , C23C16/463 , H01L33/0012 , H01L33/0033 , H01L33/0058
摘要： A method is described for fabricating electroluminescent devices exhibiting visible electroluminescence at room temperature, where the devices include at least one doped layer of amorphous hydrogenated silicon (a-Si:H). The a-Si:H layer is deposited on a substrate by homogeneous chemical vapor deposition (H-CVD) in which the substrate is held at a temperature lower than about 200.degree. C. and the a-Si:H layer is doped in-situ during deposition, the amount of hydrogen incorporated in the deposited layer being 12-50 atomic percent. The bandgap of the a-Si:H layer is between 1.6 and 2.6 eV, and in preferrable embodiments is between 2.0 and 2.6 eV. The conductivity of the a-Si:H layer is chosen in accordance with device requirements, and can be 10.sup.16 -10.sup.19 carriers/cm.sup.2. The bandgap of the a-Si:H layer depends at least in part on the temperature of the substrate on which the layer is deposited, and can be "tuned" by changing the substrate temperature.
摘要翻译： 描述了一种用于制造在室温下显示可见电致发光的电致发光器件的方法，其中器件包括至少一个非晶氢化硅掺杂层（a-Si：H）。 通过均匀化学气相沉积（H-CVD）将a-Si：H层沉积在衬底上，其中衬底保持在低于约200℃的温度，并且a-Si：H层被掺杂在 在沉积期间原位，沉积层中掺入的氢的量为12-50原子％。 a-Si：H层的带隙在1.6和2.6eV之间，优选的实施方案是在2.0和2.6eV之间。 a-Si：H层的电导率根据器件要求选择，可以为1016-1019载体/ cm2。 a-Si：H层的带隙至少部分取决于沉积该层的衬底的温度，并且可以通过改变衬底温度“调谐”。
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公开(公告)号：US4972246A
公开(公告)日：1990-11-20
申请号：US171603
申请日：1988-03-22
IPC分类号： H01L29/73 , H01L21/331 , H01L29/10 , H01L29/15 , H01L29/161 , H01L29/201 , H01L29/737
CPC分类号： H01L29/157 , H01L29/1004
摘要： A homojunction bipolar transistor having a superlattice base region comprising alternate layers of extrinsic and intrinsic layers, with extrinsic layers being of the opposite conductivity of the emitter and collector layers of the transistor. The alternate extrinsic and intrinsic layers have substantially different doping levels providing abrupt transitions in the valence and conduction bands between layers. The abrupt transitions result in the energy band gap in the base region being effectively reduced with respect to the band gap in the emitter region. In one embodiment, the effective narrow band gap base transistor is implemented by converting a portion of the upper layers of the superlattice to a homogeneous region by heavily doping the portion to form the emitter of the transistor.
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