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    Reference cells for spin torque based memory device
    1.
    发明授权
    Reference cells for spin torque based memory device 失效
    用于基于旋转扭矩的存储器件的参考单元

    公开(公告)号：US08370714B2

    公开(公告)日：2013-02-05

    申请号：US12684486

    申请日：2010-01-08

    申请人： John K. DeBrosse ,  Daniel C. Worledge

    发明人： John K. DeBrosse ,  Daniel C. Worledge

    IPC分类号： G11C29/00 ,  G11C11/00

    CPC分类号： G06F11/1048 ,  H03M13/13

    摘要： A method of reading and correcting data within a memory device that includes reading each data bit of a data word using a plurality of reference cells corresponding to each data bit, performing error detection on the read data bits, and correcting a read data bit when an error is detected using error correction code (ECC) and writing each corresponding reference cells to an original memory state thereof.

    摘要翻译： 一种在存储器件内读取和校正数据的方法，包括使用与每个数据位对应的多个参考单元读取数据字的每个数据位，对读取的数据位进行错误检测，以及当读取的数据位在 使用纠错码（ECC）检测错误，并将每个对应的参考单元写入其原始存储器状态。

    REFERENCE CELLS FOR SPIN TORQUE BASED MEMORY DEVICE
    2.
    发明申请
    REFERENCE CELLS FOR SPIN TORQUE BASED MEMORY DEVICE 失效
    基于旋转扭矩的记忆装置的参考电池

    公开(公告)号：US20110173513A1

    公开(公告)日：2011-07-14

    申请号：US12684486

    申请日：2010-01-08

    申请人： John K. DeBrosse ,  Daniel C. Worledge

    发明人： John K. DeBrosse ,  Daniel C. Worledge

    IPC分类号： H03M13/05 ,  G06F11/10

    CPC分类号： G06F11/1048 ,  H03M13/13

    摘要： A method of reading and correcting data within a memory device that includes reading each data bit of a data word using a plurality of reference cells corresponding to each data bit, performing error detection on the read data bits, and correcting a read data bit when an error is detected using error correction code (ECC) and writing each corresponding reference cells to an original memory state thereof.

    摘要翻译： 一种读取和校正存储器件内的数据的方法，包括使用对应于每个数据位的多个参考单元读取数据字的每个数据位，对读取的数据位执行错误检测，以及当读取数据位时 使用纠错码（ECC）检测错误，并将每个对应的参考单元写入其原始存储器状态。

    Spin-torque transfer magneto-resistive memory architecture
    3.
    发明授权
    Spin-torque transfer magneto-resistive memory architecture 失效
    自旋扭矩传递磁阻存储器架构

    公开(公告)号：US08456901B2

    公开(公告)日：2013-06-04

    申请号：US13559672

    申请日：2012-07-27

    申请人： John K. DeBrosse ,  Yutaka Nakamura

    发明人： John K. DeBrosse ,  Yutaka Nakamura

    IPC分类号： G11C11/00

    CPC分类号： G11C11/16 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  Y10S977/935

    摘要： A system includes a processor and a memory array connected to the processor comprising a first memory cell comprising a first magnetic tunnel junction device having a first terminal connected to a first bit line and a second terminal, and a first field effect transistor having a source terminal connected to a second bit line, a gate terminal connected to a word line, and a drain terminal connected to the second terminal of the first magnetic tunnel junction device, and a second memory cell comprising a second magnetic tunnel junction device having a first terminal connected to a third bit line and a second terminal, and a second field effect transistor having a source terminal connected to the second bit line, a gate terminal connected to the word line, and a drain terminal connected to the second terminal of the second magnetic tunnel junction device.

    摘要翻译： 一种系统包括处理器和连接到处理器的存储器阵列，该存储器阵列包括第一存储器单元，该第一存储器单元包括具有连接到第一位线的第一端子和第二端子的第一磁性隧道结器件，以及具有源极端子的第一场效应晶体管 连接到第二位线，连接到字线的栅极端子和连接到第一磁性隧道结装置的第二端子的漏极端子，以及包括第二磁性隧道结装置的第二存储单元，第二磁性隧道结装置具有第一端子连接 至第三位线和第二端子，以及第二场效应晶体管，其源极端子连接到第二位线，连接到字线的栅极端子和连接到第二磁通道的第二端子的漏极端子 连接装置。

    METHOD AND APPARATUS FOR INITIALIZING REFERENCE CELLS OF A TOGGLE SWITCHED MRAM DEVICE
    6.
    发明申请
    METHOD AND APPARATUS FOR INITIALIZING REFERENCE CELLS OF A TOGGLE SWITCHED MRAM DEVICE 失效
    用于初始化切换MRAM器件的参考电池的方法和装置

    公开(公告)号：US20080175043A1

    公开(公告)日：2008-07-24

    申请号：US11624707

    申请日：2007-01-19

    申请人： John K. DeBrosse ,  Mark C. H. Lamorey

    发明人： John K. DeBrosse ,  Mark C. H. Lamorey

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C7/14 ,  G11C11/16 ,  G11C2207/2254

    摘要： A method of determining an initial state of a reference cell in a fabricated memory array includes performing a first read operation of the reference cell by comparing current through the reference cell with the average current passing through a pair of data cells, and storing the result of the first read operation; inverting the value of one of the pair of the data cells; performing a second read operation of the reference cell, and storing the result of the second read operation; inverting the value of the other of the pair of the data cells; performing a third read operation of the reference cell, and storing the result of the third read operation. A majority compare operation of the results of the first, second and third operations is performed, wherein the result of the majority compare operation is the initial state of the reference cell.

    摘要翻译： 确定制造的存储器阵列中的参考单元的初始状态的方法包括通过将通过参考单元的电流与通过一对数据单元的平均电流进行比较来执行参考单元的第一读取操作，并且存储 第一次读取操作; 反转一对数据单元之一的值; 执行参考单元的第二读取操作，并存储第二读取操作的结果; 反转一对数据单元中的另一个的值; 执行参考单元的第三读取操作，并存储第三读取操作的结果。 执行第一，第二和第三操作的结果的多数比较操作，其中多数比较操作的结果是参考单元的初始状态。

    Method and structure for selecting anisotropy axis angle of MRAM device for reduced power consumption
    7.
    发明授权
    Method and structure for selecting anisotropy axis angle of MRAM device for reduced power consumption 失效
    用于选择MRAM器件的各向异性轴角度以降低功耗的方法和结构

    公开(公告)号：US07102916B2

    公开(公告)日：2006-09-05

    申请号：US10710281

    申请日：2004-06-30

    申请人： Philip L. Trouilloud ,  David W. Abraham ,  John K. DeBrosse ,  Daniel Worledge

    发明人： Philip L. Trouilloud ,  David W. Abraham ,  John K. DeBrosse ,  Daniel Worledge

    IPC分类号： G11C11/00

    CPC分类号： G11C11/16

    摘要： A method for determining a desired anisotropy axis angle for a magnetic random access memory (MRAM) device includes selecting a plurality of initial values for the anisotropy axis angle and determining, for each selected initial value, a minimum thickness for at least one ferromagnetic layer of the MRAM device. The minimum thickness corresponds to a predefined activation energy of an individual cell within the MRAM device. For each selected value, a minimum applied magnetic field value in a wordline direction and a bitline direction of the MRAM device is also determined so as maintain the predefined activation energy. For each selected value, an applied power per bit value is calculated, wherein the desired anisotropy axis angle is the selected anisotropy axis angle corresponding to a minimum power per bit value.

    摘要翻译： 一种用于确定磁性随机存取存储器（MRAM）装置的期望的各向异性轴角的方法包括：为各向异性轴角选择多个初始值，并为每个所选择的初始值确定至少一个铁磁层的最小厚度 MRAM设备。 最小厚度对应于MRAM设备内单个单元的预定激活能。 对于每个选择的值，还确定MRAM装置的字线方向和位线方向上的最小施加磁场值，以便维持预定的激活能量。 对于每个选择的值，计算每位值的施加功率，其中期望的各向异性轴角是对应于每位值的最小功率的所选各向异性轴角。

    Circuit configuration for a current switch of a bit/word line of a MRAM device
    8.
    发明授权
    Circuit configuration for a current switch of a bit/word line of a MRAM device 失效
    MRAM器件的位/字线的电流开关的电路配置

    公开(公告)号：US06813181B1

    公开(公告)日：2004-11-02

    申请号：US10445550

    申请日：2003-05-27

    申请人： Hans Viehmann ,  John K. DeBrosse

    发明人： Hans Viehmann ,  John K. DeBrosse

    IPC分类号： G11C1140

    CPC分类号： G11C11/16 ,  G11C7/12 ,  G11C8/08

    摘要： A circuit configuration for a current switch of a bit line or a word line of a magnetoresistive random access memory (MRAM) device, comprising a directional switch and a voltage driver that, in operation, reduces the ON resistance of the directional switch. In one embodiment, each terminal of the line is provided with such a switch.

    摘要翻译： 一种用于磁阻随机存取存储器（MRAM）器件的位线或字线的电流开关的电路配置，包括定向开关和电压驱动器，其在操作中降低了方向开关的导通电阻。 在一个实施例中，线路的每个终端设置有这样的开关。

    Four F-squared gapless dual layer bitline DRAM array architecture
    9.
    发明授权
    Four F-squared gapless dual layer bitline DRAM array architecture 有权
    四个F平方无间隙双层位线DRAM阵列架构

    公开(公告)号：US06282113B1

    公开(公告)日：2001-08-28

    申请号：US09408349

    申请日：1999-09-29

    申请人： John K. DeBrosse

    发明人： John K. DeBrosse

    IPC分类号： G11C506

    CPC分类号： G11C5/063 ,  G11C7/18 ,  G11C11/4097 ,  Y10S257/907

    摘要： A semiconductor device having a compact folded bitline architecture. Bitlines for a memory cell array arranged into bitline pairs constituting, when in use, a selected bitline and its complement. The selected bitline and its complement are adjacent in upper and lower levels, and exchange levels at selected breakpoints in the lower level bitline. The breakpoints are determined so as to establish a diagonally-oriented pattern of “twist regions” across the array. Adjacent bitline pairs exchange levels in alternating twist regions. The upper bitlines are positioned at a predetermined angle, relative to the lower bitlines, in selected intervals between the twist regions. The predetermined angle introduces an offset between the upper bitlines and their associated complement lower bitlines as the upper bitlines enter twist regions to exchange levels. The diagonal orientation of the twist regions, alternating pattern of breakpoints, and offsets eliminate gaps in the memory array which would otherwise be introduced in the twist regions, providing for enhanced cell density and a minimum cell area of approximately 4F2.

    摘要翻译： 具有紧凑折叠位线架构的半导体器件。 存储单元阵列的位线布置成位线对，在使用时构成选定的位线及其补码。 所选择的位线及其补码在上下位置相邻，并且在较低级别位线中的选定断点处的交换水平。 确定断点以便在整个阵列中建立“扭转区域”的对角线定向图案。 相邻的位线对交替扭转区域交换水平。 在扭转区域之间以选定的间隔相对于下位线将上位线定位在预定角度。 当上位线进入扭转区域以交换电平时，预定角度在上位线及其相关联的补码下位线之间引入偏移。 扭转区域的对角方向，断点的交替模式和偏移量消除了存储器阵列中的间隙，否则将在引导区域中引入，从而提供增强的单元密度和约4F2的最小单元面积。

    DRAM signal margin test method
    10.
    发明授权
    DRAM signal margin test method 失效
    DRAM信号余量测试方法

    公开(公告)号：US5610867A

    公开(公告)日：1997-03-11

    申请号：US535446

    申请日：1995-09-28

    申请人： John K. DeBrosse ,  Toshiaki Kirihata ,  Hing Wong

    发明人： John K. DeBrosse ,  Toshiaki Kirihata ,  Hing Wong

    IPC分类号： G11C11/401 ,  G11C11/409 ,  G11C11/4091 ,  G11C29/50 ,  G11C7/00 ,  G11C29/00

    CPC分类号： G11C11/4091 ,  G11C29/50 ,  G06F2201/81 ,  G11C11/401

    摘要： In the Preferred embodiment of the present invention, a bit line pair is coupled through a pair of high-resistance pass gates to a sense amp. During sense, the high-resistance pass gates act in conjunction with the charge stored on the bit line pair as, effectively, a high-resistance passive load for the sense amp. A control circuit selectively switches on and off bit line equalization coincident with selectively passing either the equalization voltage or set voltages to the sense amp and an active sense amp load. Further, after it is set, the sense amp is selectively connected to LDLs through low-resistance column select pass gates. Therefore, the sense amp quickly discharges one of the connected LDL pair while the bit line voltage remains essentially unchanged. Thus, data is passed from the sense amp to a second sense amplifier and off chip. After data is passed to the LDLs, the control circuit enables the active sense amp load to pull the sense amp high side to a full up level. Additionally, because the control circuit uses the equalization voltage to disable the sense amp, cell signal margin may be tested in a new way. Instead of varying the sense amp reference voltage, as in prior art signal margin tests, cell signal margin is tested by varying cell signal. V.sub.S may be selected to determine both a high and a low signal margin.

    摘要翻译： 在本发明的优选实施例中，位线对通过一对高电阻通过门耦合到感测放大器。 在感测期间，高电阻通过门与存储在位线对上的电荷一起作为有效地用于感测放大器的高电阻无源负载。 控制电路选择性地接通和断开位线均衡，与选择性地将均衡电压或设定电压通过感测放大器和主动感测放大器负载相一致。 此外，在设置之后，感测放大器通过低电阻列选择通孔选择性地连接到LDL。 因此，当位线电压基本保持不变时，感测放大器会快速放电连接的LDL对之一。 因此，数据从感测放大器传递到第二读出放大器和芯片外。 数据传送到LDL后，控制电路使主动感测放大器负载将感测放大器的高端拉到一个完整的电平。 此外，由于控制电路使用均衡电压来禁用读出放大器，所以可以以新的方式测试单元信号余量。 代替检测放大器参考电压，如现有技术的信号余量测试，通过改变单元信号来测试单元信号余量。 可以选择VS来确定高和低信号余量。