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1.发明申请公开(公告)号：US20110239030A1
公开(公告)日：2011-09-29
申请号：US13132097
申请日：2009-07-09
IPC分类号： G06F1/12
CPC分类号： G06F1/3237 , G06F1/12 , G06F1/3225 , G06F1/324 , G06F3/0604 , G06F3/0625 , G06F3/0629 , G06F3/0673 , G06F9/3836 , G06F12/0857 , G06F13/1689 , G06F13/36 , G06F2201/88 , G11C7/04 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C11/4096 , G11C2207/2254 , Y02D10/14
摘要： In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.
摘要翻译： 在低功率信号系统中，集成电路装置包括开环时钟分配电路和发射电路，其协作以实现不受源同步定时参考而不伴随的信息载体的高速传输。 开环时钟分配电路响应于外部提供的时钟信号而产生发送时钟信号，并且发送电路响应于发送时钟信号的转换而将符号序列输出到外部信号线上。 每个符号在符号时间的发射电路的输出端是有效的，并且发射时钟信号和外部提供的时钟信号之间的相位偏移允许至少漂移符号时间。
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公开(公告)号：US08918667B2
公开(公告)日：2014-12-23
申请号：US13132097
申请日：2009-07-09
IPC分类号： G06F1/12 , G06F13/42 , G11C11/4076 , G11C7/10 , G11C7/04 , G11C11/4096 , G11C7/22 , G06F13/16
CPC分类号： G06F1/3237 , G06F1/12 , G06F1/3225 , G06F1/324 , G06F3/0604 , G06F3/0625 , G06F3/0629 , G06F3/0673 , G06F9/3836 , G06F12/0857 , G06F13/1689 , G06F13/36 , G06F2201/88 , G11C7/04 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C11/4096 , G11C2207/2254 , Y02D10/14
摘要： In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.
摘要翻译： 在低功率信号系统中，集成电路装置包括开环时钟分配电路和发射电路，其协作以实现不受源同步定时参考而不伴随的信息载体的高速传输。 开环时钟分配电路响应于外部提供的时钟信号而产生发送时钟信号，并且发送电路响应于发送时钟信号的转换而将符号序列输出到外部信号线上。 每个符号在符号时间的发射电路的输出端是有效的，并且发射时钟信号和外部提供的时钟信号之间的相位偏移允许至少漂移符号时间。
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3.发明申请公开(公告)号：US20110239031A1
公开(公告)日：2011-09-29
申请号：US13132094
申请日：2009-07-09
IPC分类号： G06F1/00
CPC分类号： G06F1/3237 , G06F1/12 , G06F1/3225 , G06F1/324 , G06F3/0604 , G06F3/0625 , G06F3/0629 , G06F3/0673 , G06F9/3836 , G06F12/0857 , G06F13/1689 , G06F13/36 , G06F2201/88 , G11C7/04 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C11/4096 , G11C2207/2254 , Y02D10/14
摘要： In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.
摘要翻译： 在低功率信号系统中，集成电路装置包括开环时钟分配电路和发射电路，其协作以实现不受源同步定时参考而不伴随的信息载体的高速传输。 开环时钟分配电路响应于外部提供的时钟信号而产生发送时钟信号，并且发送电路响应于发送时钟信号的转换而将符号序列输出到外部信号线上。 每个符号在符号时间的发射电路的输出端是有效的，并且发射时钟信号和外部提供的时钟信号之间的相位偏移允许至少漂移符号时间。
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公开(公告)号：US20100085100A1
公开(公告)日：2010-04-08
申请号：US12525181
申请日：2008-02-12
CPC分类号： H04L25/063 , H03F3/45179 , H03F2203/45008 , H03F2203/45306 , H03F2203/45588 , H04L7/046 , H04L25/0278
摘要： A communication IC includes a power-efficient clock-distribution system. A control loop monitors and adjusts the peak and trough voltages of a clock signal. The clock signal can be adaptively adjusted to center the peak and trough voltages about the switching threshold voltage of a clock buffer. The voltage swing of the clock signal can thus be made small and, as a consequence, power efficient. The control loop can monitor and control more than one clock signal.
摘要翻译： 通信IC包括功率高效的时钟分配系统。 控制回路监视和调整时钟信号的峰值和谷底电压。 可以自适应地调整时钟信号以使峰值和谷值电压围绕时钟缓冲器的开关阈值电压。 因此，可以使时钟信号的电压摆幅变小，结果是功率有效。 控制回路可以监视和控制多个时钟信号。
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公开(公告)号：US08918669B2
公开(公告)日：2014-12-23
申请号：US13132094
申请日：2009-07-09
IPC分类号： G06F1/04 , G06F1/08 , G11C7/22 , G11C7/10 , G11C11/4076 , G11C7/04 , G11C11/4096 , G06F13/16
CPC分类号： G06F1/3237 , G06F1/12 , G06F1/3225 , G06F1/324 , G06F3/0604 , G06F3/0625 , G06F3/0629 , G06F3/0673 , G06F9/3836 , G06F12/0857 , G06F13/1689 , G06F13/36 , G06F2201/88 , G11C7/04 , G11C7/10 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C7/1078 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C7/225 , G11C11/4076 , G11C11/4096 , G11C2207/2254 , Y02D10/14
摘要： In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. The open-loop clock distribution circuit generates a transmit clock signal in response to an externally-supplied clock signal, and the transmit circuit outputs a sequence of symbols onto an external signal line in response to transitions of the transmit clock signal. Each of the symbols is valid at the output of the transmit circuit for a symbol time and a phase offset between the transmit clock signal and the externally-supplied clock signal is permitted to drift by at least the symbol time.
摘要翻译： 在低功率信号系统中，集成电路装置包括开环时钟分配电路和发射电路，其协作以实现不受源同步定时参考而不伴随的信息载体的高速传输。 开环时钟分配电路响应于外部提供的时钟信号而产生发送时钟信号，并且发送电路响应于发送时钟信号的转换而将符号序列输出到外部信号线上。 每个符号在符号时间的发射电路的输出端是有效的，并且发射时钟信号和外部提供的时钟信号之间的相位偏移允许至少漂移符号时间。
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公开(公告)号：US08310294B2
公开(公告)日：2012-11-13
申请号：US12525181
申请日：2008-02-12
IPC分类号： H03K3/00
CPC分类号： H04L25/063 , H03F3/45179 , H03F2203/45008 , H03F2203/45306 , H03F2203/45588 , H04L7/046 , H04L25/0278
摘要： A communication IC includes a power-efficient clock-distribution system. A control loop monitors and adjusts the peak and trough voltages of a clock signal. The clock signal can be adaptively adjusted to center the peak and trough voltages about the switching threshold voltage of a clock buffer. The voltage swing of the clock signal can thus be made small and, as a consequence, power efficient. The control loop can monitor and control more than one clock signal.
摘要翻译： 通信IC包括功率高效的时钟分配系统。 控制回路监视和调整时钟信号的峰值和谷底电压。 可以自适应地调整时钟信号以使峰值和谷值电压围绕时钟缓冲器的开关阈值电压。 因此，可以使时钟信号的电压摆幅变小，结果是功率有效。 控制回路可以监视和控制多个时钟信号。
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公开(公告)号：US20100309791A1
公开(公告)日：2010-12-09
申请号：US12745489
申请日：2008-12-02
申请人： Andrew M. Fuller , John W. Poulton
发明人： Andrew M. Fuller , John W. Poulton
IPC分类号： H04J3/14
CPC分类号： H04L25/0262 , H04L1/20 , H04L1/246
摘要： Systems and methods are provided for edge-based loss-of-signal (LOS) detection. In a receiver, a receiver port receives a data signal. A clock and data recovery (CDR) mechanism coupled to the receive port derives one or more clock signals. An LOS signal generation mechanism generates an LOS signal based on edge glitches which occur when the receive port does not receive usable data.
摘要翻译： 为基于边缘的信号丢失（LOS）检测提供了系统和方法。 在接收机中，接收端口接收数据信号。 耦合到接收端口的时钟和数据恢复（CDR）机制导出一个或多个时钟信号。 LOS信号产生机制基于接收端口不接收可用数据时出现的边缘毛刺产生LOS信号。
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公开(公告)号：US08509094B2
公开(公告)日：2013-08-13
申请号：US12745489
申请日：2008-12-02
申请人： Andrew M. Fuller , John W. Poulton
发明人： Andrew M. Fuller , John W. Poulton
IPC分类号： G01R31/08
CPC分类号： H04L25/0262 , H04L1/20 , H04L1/246
摘要： Systems and methods are provided for edge-based loss-of-signal (LOS) detection. In a receiver, a receiver port receives a data signal. A clock and data recovery (CDR) mechanism coupled to the receive port derives one or more clock signals. An LOS signal generation mechanism generates an LOS signal based on edge glitches which occur when the receive port does not receive usable data.
摘要翻译： 为基于边缘的信号丢失（LOS）检测提供了系统和方法。 在接收机中，接收端口接收数据信号。 耦合到接收端口的时钟和数据恢复（CDR）机制导出一个或多个时钟信号。 LOS信号产生机制基于接收端口不接收可用数据时出现的边缘毛刺产生LOS信号。
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公开(公告)号：US20100220828A1
公开(公告)日：2010-09-02
申请号：US12525044
申请日：2008-02-11
申请人： Andrew M. Fuller , John Poulton
发明人： Andrew M. Fuller , John Poulton
IPC分类号： H04L7/00
CPC分类号： H04L25/063 , H03F3/45179 , H03F2203/45008 , H03F2203/45306 , H03F2203/45588 , H04L7/046 , H04L25/0278
摘要： Embodiments of a circuit are described. This circuit includes a receiver circuit including a first sampler (312-1) and a second” sampler (312-2). A clock-data-recovery circuit (324) in the receiver circuit adjusts a sample time of the receiver circuit so that the sample time is proximate to a signal crossing point at an edge of an eye pattern associated with received signals. An offset-calibration circuit (326) in the receiver circuit determines and adjusts an offset voltage of a given sampler, which can be the first sampler or the second sampler. This offset-calibration circuit may determine a present offset voltage (412) of the given sampler in a timing region proximate to the signal crossing point (410-2) in which the clock-data-recovery circuit dithers about a present sample time based on the present offset voltage. Additionally, the clock-data-recovery circuit and the offset-calibration circuit may iteratively converge on the signal crossing point and a residual offset voltage of the given sampler.
摘要翻译： 描述电路的实施例。 该电路包括包括第一采样器（312-1）和第二“采样器（312-2）”的接收器电路。 接收器电路中的时钟数据恢复电路（324）调整接收器电路的采样时间，使得采样时间接近与接收信号相关联的眼图的边缘处的信号交叉点。 接收器电路中的偏移校准电路（326）确定并调整给定采样器的偏移电压，其可以是第一采样器或第二采样器。 该偏移校准电路可以在靠近信号交叉点（410-2）的定时区域中确定给定采样器的当前偏移电压（412），其中时钟数据恢复电路基于当前采样时间抖动 当前偏移电压。 此外，时钟数据恢复电路和偏移校准电路可以迭代地收敛于给定采样器的信号交叉点和剩余偏移电压。
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公开(公告)号：US08199866B2
公开(公告)日：2012-06-12
申请号：US12525044
申请日：2008-02-11
申请人： Andrew M. Fuller , John Poulton
发明人： Andrew M. Fuller , John Poulton
IPC分类号： H04L7/00
CPC分类号： H04L25/063 , H03F3/45179 , H03F2203/45008 , H03F2203/45306 , H03F2203/45588 , H04L7/046 , H04L25/0278
摘要： Embodiments of a circuit are described. This circuit includes a receiver circuit including a first sampler (312-1) and a second” sampler (312-2). A clock-data-recovery circuit (324) in the receiver circuit adjusts a sample time of the receiver circuit so that the sample time is proximate to a signal crossing point at an edge of an eye pattern associated with received signals. An offset-calibration circuit (326) in the receiver circuit determines and adjusts an offset voltage of a given sampler, which can be the first sampler or the second sampler. This offset-calibration circuit may determine a present offset voltage (412) of the given sampler in a timing region proximate to the signal crossing point (410-2) in which the clock-data-recovery circuit dithers about a present sample time based on the present offset voltage. Additionally, the clock-data-recovery circuit and the offset-calibration circuit may iteratively converge on the signal crossing point and a residual offset voltage of the given sampler.
摘要翻译： 描述电路的实施例。 该电路包括包括第一采样器（312-1）和第二“采样器（312-2）”的接收器电路。 接收器电路中的时钟数据恢复电路（324）调整接收器电路的采样时间，使得采样时间接近与接收信号相关联的眼图的边缘处的信号交叉点。 接收器电路中的偏移校准电路（326）确定并调整给定采样器的偏移电压，其可以是第一采样器或第二采样器。 该偏移校准电路可以在靠近信号交叉点（410-2）的定时区域中确定给定采样器的当前偏移电压（412），其中时钟数据恢复电路基于当前采样时间抖动 当前偏移电压。 此外，时钟数据恢复电路和偏移校准电路可以迭代地收敛于给定采样器的信号交叉点和剩余偏移电压。
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