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1.发明授权Heterostructure field effect device having refractory ohmic contact directly on channel layer and method for making 失效异质结构场效应器件直接在通道层上具有难熔欧姆接触和制造方法
公开(公告)号：US5606184A
公开(公告)日：1997-02-25
申请号：US434867
申请日：1995-05-04
申请人： Jonathan K. Abrokwah , Jenn-Hwa Huang , William J. Ooms , Carl L. Shurboff , Jerald A. Hallmark
发明人： Jonathan K. Abrokwah , Jenn-Hwa Huang , William J. Ooms , Carl L. Shurboff , Jerald A. Hallmark
IPC分类号： H01L29/43 , H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/335 , H01L21/338 , H01L23/52 , H01L27/085 , H01L29/08 , H01L29/417 , H01L29/45 , H01L29/778 , H01L29/812 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/66462 , H01L21/28575 , H01L27/085 , H01L29/0891 , H01L29/41766 , H01L29/452
摘要： A complementary III-V heterostructure field effect device includes the same refractory ohmic material for providing the contacts (117, 119), to both the N-type and P-type devices. Furthermore, the refractory ohmic contacts (117, 119) directly contact the InGaAs channel layer (16) to provide improved ohmic contact, despite the fact that the structure incorporates an advantageous high aluminum composition barrier layer (18) and an advantageous GaAs cap layer (20).
摘要翻译： 互补的III-V异质结构场效应器件包括用于向N型和P型器件提供触点（117,119）的相同难熔欧姆材料。 此外，难熔欧姆接触（117,119）直接接触InGaAs沟道层（16）以提供改善的欧姆接触，尽管该结构包含有利的高铝成分阻挡层（18）和有利的GaAs覆盖层（ 20）。
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2.发明授权Method of making a III-V complementary heterostructure device with compatible non-gold ohmic contacts 失效制造具有兼容的非金欧姆接触的III-V互补异质结构器件的方法
公开(公告)号：US5480829A
公开(公告)日：1996-01-02
申请号：US83755
申请日：1993-06-25
CPC分类号： H01L29/66462 , H01L27/0605 , H01L29/452
摘要： The present invention encompasses a complementary semiconductor device having the same type of material providing the ohmic contacts (117, 119) to both the N-type and P-type devices. In a preferred embodiment, P-source and P -drain regions ( 80, 82 ) are heavily doped with a P-type impurity (81, 83) so that an ohmic with N-type impurity can be used as an ohmic contact. One ohmic material that may be used is nickel-germanium-tungsten. Nickel-germanium-tungsten is etchable, and therefore does not require lift-off processing. Furthermore, a preferred complementary semiconductor device made in accordance with the present invention is compatible with modern aluminum based VLSI interconnection processes.
摘要翻译： 本发明包括具有向N型和P型器件提供欧姆接触（117,119）的相同类型材料的互补半导体器件。 在优选实施例中，P源极和P区域（80,82）被P型杂质（81,83）重掺杂，使得具有N型杂质的欧姆可以用作欧姆接触。 可以使用的一种欧姆材料是镍 - 锗 - 钨。 镍锗钨是可蚀刻的，因此不需要剥离处理。 此外，根据本发明制造的优选的互补半导体器件与现代的基于铝的VLSI互连工艺兼容。
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公开(公告)号：US5739557A
公开(公告)日：1998-04-14
申请号：US384050
申请日：1995-02-06
申请人： Vernon Patrick O'Neil, II , Jonathan K. Abrokwah , Majid M. Hashemi , Jenn-Hwa Huang , Vijay K. Nair , Farideh Nikpourian , Saied Nikoo Tehrani
发明人： Vernon Patrick O'Neil, II , Jonathan K. Abrokwah , Majid M. Hashemi , Jenn-Hwa Huang , Vijay K. Nair , Farideh Nikpourian , Saied Nikoo Tehrani
IPC分类号： H01L29/41 , H01L21/285 , H01L21/335 , H01L21/338 , H01L21/76 , H01L21/8252 , H01L29/45 , H01L29/47 , H01L29/778 , H01L29/812 , H01L29/872 , H01L31/0328 , H01L31/0336
CPC分类号： H01L29/66462 , H01L21/28575 , H01L21/28581 , H01L21/8252 , H01L29/452 , H01L29/475 , H01L29/7783
摘要： A heterostructure field effect transistor and method including at least one passivation layer (20) and at least one etch stop layer (22). Enhancement, depletion and combined devices with both enhancement mode and depletion mode devices are possible with minor process variations. Refractory gate (40) and non-gold refractory ohmic contact (52) metallization combined with other features allows non-liftoff metal patterning.
摘要翻译： 一种异质结构场效应晶体管和方法，包括至少一个钝化层（20）和至少一个蚀刻停止层（22）。 增强，耗尽以及增强模式和耗尽模式设备的组合设备都可能具有较小的过程变化。 耐火门（40）和非金难熔欧姆接触（52）金属化结合其他特征允许非剥离金属图案化。
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公开(公告)号：US5116774A
公开(公告)日：1992-05-26
申请号：US673438
申请日：1991-03-22
IPC分类号： H01L21/8252 , H01L27/06 , H01L27/092 , H01L29/80
CPC分类号： H01L29/802 , H01L21/8252 , H01L27/0605 , H01L27/092 , Y10S148/053 , Y10S148/072
摘要： A method of fabricating heterojunction structures includes providing a semiconductor substrate and forming a plurality of semiconductor layers thereon. Ohmic and gate contacts are then formed on the plurality of semiconductor layers and portions of at least one of the semiconductor layers disposed between the ohmic and gate contacts are removed. Gate metal is then formed on the gate contacts. Source and drain regions are formed in the semiconductor layers and the formation is self-aligned to the gate metal. Following the formation of the source and drain regions, ohmic metal is formed on the ohmic contacts.
摘要翻译： 制造异质结结构的方法包括提供半导体衬底并在其上形成多个半导体层。 然后在多个半导体层上形成欧姆和栅极触点，并且去除设置在欧姆与栅极触点之间的至少一个半导体层的部分。 然后在栅极触点上形成栅极金属。 源区和漏区形成在半导体层中，并且形成与栅极金属自对准。 在形成源区和漏极区之后，在欧姆接触上形成欧姆金属。
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5.发明授权Method of making ohmic contacts to a complementary III-V semiconductor device 失效向互补的III-V半导体器件制造欧姆接触的方法
公开(公告)号：US5444016A
公开(公告)日：1995-08-22
申请号：US83751
申请日：1993-06-25
IPC分类号： H01L21/285 , H01L21/335 , H01L21/8238 , H01L29/45 , H01L21/44 , H01L21/48
CPC分类号： H01L29/66462 , H01L21/28575 , H01L21/823871 , H01L29/452 , Y10S148/02 , Y10S148/065
摘要： The present invention encompasses a method for providing the same ohmic material contact (120, 122, 124) to N-type and P-type regions (70, 80) of a III-V semiconductor device. Specifically, an N-type region (70) extending through a semiconductor structure is formed. Additionally, a P-type region (80) extending through the substrate is formed. The P-type region (80) may be heavily doped with P-type impurities (81). A first ohmic region (117) is formed, contacting the N-type region (70). The first ohmic region may comprise an ohmic material including metal and an N-type dopant. A second ohmic region (119) is formed, contacting the P-type region (80, 81). The second ohmic region comprises the same ohmic material as the first ohmic region. One ohmic material that may be used is nickel-germanium-tungsten.
摘要翻译： 本发明包括用于向III-V半导体器件的N型和P型区（70,80）提供相同的欧姆材料接触（120,122,124）的方法。 具体地，形成延伸穿过半导体结构的N型区域（70）。 此外，形成延伸穿过衬底的P型区域（80）。 P型区域（80）可以重掺杂P型杂质（81）。 形成与N型区域（70）接触的第一欧姆区域（117）。 第一欧姆区域可以包括包括金属和N型掺杂剂的欧姆材料。 形成与P型区域（80,81）接触的第二欧姆区域（119）。 第二欧姆区域包括与第一欧姆区域相同的欧姆材料。 可以使用的一种欧姆材料是镍 - 锗 - 钨。
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6.发明授权Complementary heterojunction field effect transistor with an anisotype N+ g a -channel devices 失效用于P沟道器件的互补异质结场效应晶体管具有N型栅极
公开(公告)号：US5060031A
公开(公告)日：1991-10-22
申请号：US584014
申请日：1990-09-18
IPC分类号： H01L29/812 , H01L21/338 , H01L27/085 , H01L29/778 , H01L29/80
CPC分类号： H01L27/085 , H01L29/802
摘要： A GaAs complementary HFET structure having an anisotype layer formed underneath the P-channel device gate is provided. The anisotype layer is heavily doped N-type and is formed in contact with a semi-insulating AlGaAs barrier of the P-channel FET. A pre-ohmic layer is formed over the anisotype layer and a gate electrode is formed over the pre-ohmic layer. In a first embodiment, the pre-ohmic layer comprises undoped gallium arsenide amd the gate electrode forms a Schottky diode with the pre-ohmic layer. The anisotype layer forms a semiconductor junction with the semi-insulating AlGaAs barrier wherein the semiconductor junction replaces or augments a conventional Schottky junction. In a second embodiment, the pre-ohmic layer comprises heavily doped InGaAs and the gate electrode forms an ohmic contact to the doped InGaAs. The semiconductor junction at the P-channel device gate results in higher built in potential barrier and improved P-channel gate turn on voltage.
摘要翻译： 提供了具有形成在P沟道器件栅极下方的异型层的GaAs互补HFET结构。 异型层是重掺杂的N型，并且形成为与P沟道FET的半绝缘AlGaAs势垒接触。 在异型层之上形成前欧姆层，并且在前欧姆层上形成栅电极。 在第一实施例中，前欧姆层包括未掺杂的砷化镓，栅极与反欧姆层形成肖特基二极管。 异型层与半绝缘AlGaAs屏障形成半导体结，其中半导体结替代或增强常规的肖特基结。 在第二实施例中，前欧姆层包括重掺杂的InGaAs，并且栅电极与掺杂的InGaAs形成欧姆接触。 P沟道器件栅极的半导体结导致较高的内置势垒和改进的P沟道栅极导通电压。
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公开(公告)号：US6091621A
公开(公告)日：2000-07-18
申请号：US985456
申请日：1997-12-05
申请人： Yang Wang , Jenn-Hwa Huang , Kurt Eisenbeiser , Ellen Lan , William J. Ooms
发明人： Yang Wang , Jenn-Hwa Huang , Kurt Eisenbeiser , Ellen Lan , William J. Ooms
CPC分类号： G11C11/22 , G11C11/5657
摘要： A multi-state non-volatile ferroelectric memory includes a field effect transistor having a gate insulator formed of ferroelectric material. The ferroelectric material is separated into regions of different characteristics, e.g. different thicknesses, different coercive field values, etc., so as to provide a plurality of different threshold voltages for the field effect transistor.
摘要翻译： 多状态非易失性铁电存储器包括具有由铁电材料形成的栅极绝缘体的场效应晶体管。 铁电材料被分成不同特性的区域，例如 不同的厚度，不同的矫顽场值等，以便为场效应晶体管提供多个不同的阈值电压。
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公开(公告)号：US5719088A
公开(公告)日：1998-02-17
申请号：US556477
申请日：1995-11-13
申请人： Jenn-Hwa Huang , Mark Durlam , Marino J. Martinez , Ernie Schirmann , Saied N. Tehrani , William J. Ooms
发明人： Jenn-Hwa Huang , Mark Durlam , Marino J. Martinez , Ernie Schirmann , Saied N. Tehrani , William J. Ooms
IPC分类号： H01L21/285 , H01L21/311 , H01L21/335 , H01L23/485 , H01L21/44
CPC分类号： H01L29/66462 , H01L21/28587 , H01L21/31116 , H01L23/485 , H01L2924/0002
摘要： A method of fabricating semiconductor devices with a passivated surface includes providing a contact layer on a substrate so as to define an inter-electrode surface area. A first layer and an insulating layer, which are selectively etchable relative to each other and to the substrate and the contact layer, are deposited on the contact layer and the inter-electrode surface area. The insulating layer and the first layer are individually and selectively etched to define an electrode contact area and to expose the inter-electrode surface area. The exposed inter-electrode surface area is passivated, either subsequent to or during the etching of the first layer. A metal contact is formed in the electrode contact area in abutting engagement with the insulating layer so as to seal the inter-electrode surface area.
摘要翻译： 制造具有钝化表面的半导体器件的方法包括在衬底上提供接触层以便限定电极间表面积。 可以相对于彼此和基板和接触层选择性地蚀刻的第一层和绝缘层沉积在接触层和电极间表面区域上。 分别选择性地蚀刻绝缘层和第一层以限定电极接触面积并暴露电极间表面积。 暴露的电极间表面积在第一层蚀刻之前或期间被钝化。 在与绝缘层邻接的电极接触区域中形成金属接触，以密封电极间表面积。
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9.发明授权MEMS variable capacitor with stabilized electrostatic drive and method therefor 有权具有稳定静电驱动的MEMS可变电容器及其方法公开(公告)号：US06441449B1
公开(公告)日：2002-08-27
申请号：US09981014
申请日：2001-10-16
IPC分类号： H01L2100
CPC分类号： H01H59/0009 , H01G5/16
摘要： A micro electro-mechanical systems device having variable capacitance is controllable over the full dynamic range and not subject to the “snap effect” common in the prior art. The device features an electrostatic driver (120) having a driver capacitor of fixed capacitance (121) in series with a second driver capacitor of variable capacitance (126). A MEMS variable capacitor (130) is controlled by applying an actuation voltage potential to the electrostatic driver (120). The electrostatic driver (120) and MEMS variable capacitor (130) are integrated in a single, monolithic device.
摘要翻译： 具有可变电容的微机电系统装置在整个动态范围内是可控的，并且不受现有技术中常见的“卡扣效应”的制约。 该装置具有静电驱动器（120），其具有与可变电容（126）的第二驱动电容器串联的具有固定电容的驱动电容器（121）。 通过向静电驱动器（120）施加致动电压电位来控制MEMS可变电容器（130）。 静电驱动器（120）和MEMS可变电容器（130）集成在单个单片器件中。
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公开(公告)号：US06307169B1
公开(公告)日：2001-10-23
申请号：US09495664
申请日：2000-02-01
IPC分类号： H01H5700
CPC分类号： B81B3/0008 , B81B2201/018 , B81B2203/0361 , H01H59/0009 , H01H2001/0089 , H01H2059/0054 , H01H2059/0072 , H01P1/12
摘要： A Micro-Electromechanical System (MEMS) switch (100) having a single, center hinge (120) which supports a membrane-type electrode (104) on a substrate (101). The single, center hinge (120) has a control electrode (104) coupled to the substrate (101) by an anchor (113), a hinge collar (121), a set of hinge arms (122, 123). The control electrode (104) has a shorting bar (106) coupled thereto and is electrically isolated from another control electrode (105), which is formed on the substrate (101). A travel stop (130) is positioned between the substrate and the control electrode (104). Another aspect of the present invention is a Single Pole, Double Throw (SPDT) switch (160) into which is incorporated the single, center hinge (170) and the travel stop (185, 186).
摘要翻译： 具有在基板（101）上支撑膜型电极（104）的单个中心铰链（120）的微机电系统（MEMS）开关（100）。 单个中心铰链（120）具有通过锚固件（113），铰链轴环（121），一组铰链臂（122,123）联接到基板（101）的控制电极（104）。 控制电极（104）具有与其耦合的短路棒（106），并与形成在基板（101）上的另一个控制电极（105）电隔离。 移动停止件（130）位于基板和控制电极（104）之间。 本发明的另一方面是单杆双掷（SPDT）开关（160），其中并入有单个中心铰链（170）和行驶停止件（185,186）。
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