公开(公告)号：US20240123054A1

公开(公告)日：2024-04-18

申请号：US18277536

申请日：2022-02-18

申请人： Joseph COTROPIA ,  Gaurav Chandra

发明人： Joseph COTROPIA ,  Gaurav Chandra

IPC分类号： A61K39/215 ,  C07K16/10

CPC分类号： A61K39/215 ,  C07K16/1003 ,  C07K2317/34 ,  C07K2317/76

摘要： Provided are highly conserved antigens and epitopes of SARS-CoV-2 that can be used in vaccines and to produce bindings proteins (e.g., antibodies) for treating, preventing, or reducing the risks of infections caused by β-coronaviruses such as SARS-CoV-2, and as targets for detecting SARS-CoV-2 infection

公开(公告)号：US07327997B2

公开(公告)日：2008-02-05

申请号：US10711724

申请日：2004-09-30

申请人： Gaurav Chandra ,  Preetam Charan Anand Tadeparthy ,  Prakash Easwaran

发明人： Gaurav Chandra ,  Preetam Charan Anand Tadeparthy ,  Prakash Easwaran

IPC分类号： H04B1/10

CPC分类号： H03H11/126 ,  H04B1/16

摘要： A trans-impedance filter circuit provided according to an aspect of the present invention contains an operational amplifier, a first resistor, a first capacitor, a second resistor, and a second capacitor. The second capacitor is connected in parallel between the inverting input terminal and an output path of the operational amplifier. The second resistor is connected between the output terminal of the operational amplifier and a second node on a path connecting the input signal to the inverting input terminal. The first resistor is coupled between the first node and inverting input terminal of the operational amplifier. The first capacitor is coupled between the first node and Vss. Due to such connections, the filter circuit operates as a second order filter circuit, thereby providing a desired high level of filtering. Also, as the filter circuit is implemented with a single operational amplifier, the power and area requirements are reduced.

摘要翻译： 根据本发明一方面提供的跨阻抗滤波器电路包括运算放大器，第一电阻器，第一电容器，第二电阻器和第二电容器。 第二电容器并联连接在反相输入端和运算放大器的输出路径之间。 第二电阻器连接在运算放大器的输出端和将输入信号连接到反相输入端的路径上的第二节点之间。 第一电阻耦合在运算放大器的第一节点和反相输入端之间。 第一电容器耦合在第一节点和Vss之间。 由于这种连接，滤波器电路作为二阶滤波器电路工作，从而提供期望的高级滤波。 而且，由于滤波器电路由单个运算放大器实现，所以功率和面积要求降低。

公开(公告)号：US20100259429A1

公开(公告)日：2010-10-14

申请号：US12423667

申请日：2009-04-14

申请人： Baher Haroun ,  Gaurav Chandra

发明人： Baher Haroun ,  Gaurav Chandra

IPC分类号： H03M1/10 ,  H03M1/66

CPC分类号： H03M1/1033 ,  H03M1/747

摘要： Methods and apparatus for error cancelation in calibrated current sources are disclosed. In an example, a digital to analog converter to convert digital bits into an analog output signal is described, including a plurality of current sources, a calibrator, and a current source selector. The example current sources output substantially identical currents, and the calibrator is selectively coupled to sequentially calibrate the current sources to a reference current. The example current source selector assigns respective ones of the plurality of current sources to the digital bits in accordance with a bit-to-current source sequence selected to reduce current error in the analog output and changes the assignments based on the current source coupled to the calibrator.

摘要翻译： 公开了用于校准电流源中的误差消除的方法和装置。 在一个示例中，描述了将数字位转换为模拟输出信号的数模转换器，包括多个电流源，校准器和电流源选择器。 示例性电流源输出基本相同的电流，并且校准器被选择性地耦合以将电流源依次校准为参考电流。 示例性电流源选择器根据选择以减少模拟输出中的电流误差的位电流源序列将多个电流源中的相应电流源分配给数字位，并且基于耦合到 校准器

公开(公告)号：US07804433B1

公开(公告)日：2010-09-28

申请号：US12423667

申请日：2009-04-14

申请人： Baher Haroun ,  Gaurav Chandra

发明人： Baher Haroun ,  Gaurav Chandra

IPC分类号： H03M1/10

CPC分类号： H03M1/1033 ,  H03M1/747

摘要： Methods and apparatus for error cancelation in calibrated current sources are disclosed. In an example, a digital to analog converter to convert digital bits into an analog output signal is described, including a plurality of current sources, a calibrator, and a current source selector. The example current sources output substantially identical currents, and the calibrator is selectively coupled to sequentially calibrate the current sources to a reference current. The example current source selector assigns respective ones of the plurality of current sources to the digital bits in accordance with a bit-to-current source sequence selected to reduce current error in the analog output and changes the assignments based on the current source coupled to the calibrator.

摘要翻译： 公开了用于校准电流源中的误差消除的方法和装置。 在一个示例中，描述了将数字位转换为模拟输出信号的数模转换器，包括多个电流源，校准器和电流源选择器。 示例性电流源输出基本相同的电流，并且校准器被选择性地耦合以将电流源依次校准为参考电流。 示例性电流源选择器根据选择以减少模拟输出中的电流误差的位电流源序列将多个电流源中的相应电流源分配给数字位，并且基于耦合到 校准器

公开(公告)号：US07915905B2

公开(公告)日：2011-03-29

申请号：US12761544

申请日：2010-04-16

申请人： Baher S. Haroun ,  Gaurav Chandra ,  Vijaya Bhaskar Rentala ,  Venkatesh Srinivasan ,  Hisashi Shichijo ,  Krishnaswamy Nagaraj

发明人： Baher S. Haroun ,  Gaurav Chandra ,  Vijaya Bhaskar Rentala ,  Venkatesh Srinivasan ,  Hisashi Shichijo ,  Krishnaswamy Nagaraj

IPC分类号： G01R31/00

CPC分类号： H03M3/35 ,  H01L22/34 ,  H03M3/43 ,  H03M3/438

摘要： In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defeats are within an allowable range.

摘要翻译： 在用于监测晶片中的缺陷的装置和方法中，在每个晶片的区域上制造监视电路。 监测电路包括代表位于晶片的管芯区域中的类似器件的代表性器件。 如果存在于代表性装置中的缺陷有助于产生噪声，从而导致在所选代表装置中可测量的差分信号的不平衡。 使用共模电压作为参考来测量不平衡的数字化电路将差分信号数字化为数字信号，数字信号表示由缺陷产生的噪声。 数字信号以可配置的时间间隔存储以形成数字比特流。 将数字比特流与参考进行比较，以确定失败是否在允许的范围内。

公开(公告)号：US07642852B2

公开(公告)日：2010-01-05

申请号：US12109449

申请日：2008-04-25

申请人： Gaurav Chandra ,  Danielle Lyn Griffith

发明人： Gaurav Chandra ,  Danielle Lyn Griffith

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F3/45659 ,  H03F2203/45048 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45438 ,  H03F2203/45534 ,  H03F2203/45686 ,  H03F2203/45702

摘要： In a method and apparatus for trimming values of load resistors to reduce variations there between, a common mode feedback loop (CMFBL) included in a differential amplifier is switched from operating in a closed loop mode to operate in an open loop mode. The CMFBL includes an operational amplifier (OA) generating an output signal. A selector switch, coupled to receive the output signal, is operable to switch a path of the output signal in response to a CAL signal. In the closed loop mode, the selector switch routes the output signal to a feedback loop to provide a regulated current to the load resistors. In the open loop mode, the OA operates as a comparator and the output signal is provided as a digital signal. The selector switch provides the digital signal to a controller to digitally trim the values of the load resistors.

摘要翻译： 在用于修整负载电阻器的值以减小其间的变化的方法和装置中，包括在差分放大器中的共模反馈环路（CMFBL）从闭环模式中操作切换到以开环模式操作。 CMFBL包括产生输出信号的运算放大器（OA）。 耦合以接收输出信号的选择器开关可用于响应于CAL信号切换输出信号的路径。 在闭环模式下，选择器开关将输出信号路由到反馈回路，以向负载电阻提供稳压电流。 在开环模式下，OA作为比较器运行，输出信号作为数字信号提供。 选择器开关为控制器提供数字信号，以数字修整负载电阻的值。

公开(公告)号：US20090251164A1

公开(公告)日：2009-10-08

申请号：US12061409

申请日：2008-04-02

申请人： Baher S. Haroun ,  Gaurav Chandra ,  Vijaya Bhaskar Rentala ,  Venkatesh Srinivasan ,  Hisashi Shichijo ,  Krishnaswamy Nagaraj

发明人： Baher S. Haroun ,  Gaurav Chandra ,  Vijaya Bhaskar Rentala ,  Venkatesh Srinivasan ,  Hisashi Shichijo ,  Krishnaswamy Nagaraj

IPC分类号： H01L21/66 ,  H03M3/00

CPC分类号： H03M3/35 ,  H01L22/34 ,  H03M3/43 ,  H03M3/438

摘要： In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defects are within an allowable range.

摘要翻译： 在用于监测晶片中的缺陷的装置和方法中，在每个晶片的区域上制造监视电路。 监测电路包括代表位于晶片的管芯区域中的类似器件的代表性器件。 如果存在于代表性装置中的缺陷有助于产生噪声，从而导致在所选代表装置中可测量的差分信号的不平衡。 使用共模电压作为参考来测量不平衡的数字化电路将差分信号数字化为数字信号，数字信号表示由缺陷产生的噪声。 数字信号以可配置的时间间隔存储以形成数字比特流。 将数字位流与参考值进行比较，以确定缺陷是否在允许范围内。

公开(公告)号：US20090096648A1

公开(公告)日：2009-04-16

申请号：US11974142

申请日：2007-10-11

申请人： Gaurav Chandra

发明人： Gaurav Chandra

IPC分类号： H03M3/00

CPC分类号： H03M1/0663 ,  H03M3/346 ,  H03M3/464

摘要： In an apparatus and method for improving performance of a third order, double-sampled, sigma-delta modulator (SDM), a first one of three feedback elements included in a feedback loop of the SDM is selected to complete the feedback loop during a first half-cycle of the clock used for the double-sampling. The first one is restricted from being reselected during a subsequent half-cycle of the clock until the first one is reset. A second one of the three feedback elements is selected during a second half-cycle of the clock that is consecutive to the first half-cycle, the second one being different than the first one. A third one of the three feedback elements is selected during a third half-cycle of the clock that is consecutive to the second half-cycle, the third one being different than the second one.

摘要翻译： 在用于改善三阶双倍采样，Σ-Δ调制器（SDM）的性能的装置和方法中，选择包括在SDM的反馈环路中的三个反馈元件中的第一个，以在第一次 用于双采样的时钟半周期。 第一个在时钟的后续半周期被限制重新选择，直到第一个复位为止。 在与第一半周期连续的时钟的第二半周期期间选择三个反馈元件中的第二个，第二个与第一个半周期不同。 在与第二半周期连续的时钟的第三半周期期间选择三个反馈元件中的第三个，第三个与第二个半周期不同。

公开(公告)号：US07508330B1

公开(公告)日：2009-03-24

申请号：US11974142

申请日：2007-10-11

申请人： Gaurav Chandra

发明人： Gaurav Chandra

IPC分类号： H03M3/00

CPC分类号： H03M1/0663 ,  H03M3/346 ,  H03M3/464

摘要： In an apparatus and method for improving performance of a third order, double-sampled, sigma-delta modulator (SDM), a first one of three feedback elements included in a feedback loop of the SDM is selected to complete the feedback loop during a first half-cycle of the clock used for the double-sampling. The first one is restricted from being reselected during a subsequent half-cycle of the clock until the first one is reset. A second one of the three feedback elements is selected during a second half-cycle of the clock that is consecutive to the first half-cycle, the second one being different than the first one. A third one of the three feedback elements is selected during a third half-cycle of the clock that is consecutive to the second half-cycle, the third one being different than the second one.

摘要翻译： 在用于改善三阶双倍采样，Σ-Δ调制器（SDM）的性能的装置和方法中，选择包括在SDM的反馈环路中的三个反馈元件中的第一个，以在第一次 用于双采样的时钟半周期。 第一个在时钟的后续半周期被限制重新选择，直到第一个复位为止。 在与第一半周期连续的时钟的第二半周期期间选择三个反馈元件中的第二个，第二个与第一个半周期不同。 在与第二半周期连续的时钟的第三半周期期间选择三个反馈元件中的第三个，第三个与第二个半周期不同。

公开(公告)号：US07002506B1

公开(公告)日：2006-02-21

申请号：US10905271

申请日：2004-12-23

申请人： Preetam Charan Anand Tadeparthy ,  Jomy G Joy ,  Gaurav Chandra ,  Sumeet Mathur

发明人： Preetam Charan Anand Tadeparthy ,  Jomy G Joy ,  Gaurav Chandra ,  Sumeet Mathur

IPC分类号： H03M1/38 ,  H03M1/00 ,  G11C27/02 ,  H03K17/00 ,  H03K5/00

CPC分类号： H03M1/0607 ,  H03M1/167 ,  H03M1/804

摘要： A pipeline ADC implemented with both general charge redistribution stages and flip-around charge redistribution stages. Using the flip-around charge redistribution stages leads to reduced power/area consumption, but could lead to accumulation and propagation of errors. general charge redistribution stages are used to control/contain the errors. As a result, the ADC is implemented to achieve an acceptable bit error and power efficiency combination. According to another aspect of the present invention, the first stage is implemented as a flip-around charge redistribution stage (in combination with general charge redistribution stages in subsequent stages) since there is no accumulation of error from prior stages, and implementing the first stage as a flip-around charge redistribution stage gives maximum advantages in power efficiency.

摘要翻译： 采用一般电荷再分配阶段和翻转电荷再分配阶段实现的流水线ADC。 使用翻转电荷再分配阶段导致功率/面积消耗降低，但可能导致误差的累积和传播。 一般电荷再分配阶段用于控制/包含错误。 因此，实现了ADC以实现可接受的位错误和功率效率组合。 根据本发明的另一方面，第一级被实现为翻转电荷再分配阶段（与随后阶段中的一般电荷再分配阶段相结合），因为不存在来自前一级的误差累积，并且实现第一级 作为翻转充电再分配阶段在功率效率方面给出最大的优势。