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    Semiconductor memory device having high capacitance and improved radiation immunity
    2.
    发明授权
    Semiconductor memory device having high capacitance and improved radiation immunity 失效
    半导体存储器件具有高电容和改善的辐射抗扰性

    公开(公告)号：US4833647A

    公开(公告)日：1989-05-23

    申请号：US903997

    申请日：1986-09-05

    申请人： Satoshi Maeda ,  Shizuo Sawada

    发明人： Satoshi Maeda ,  Shizuo Sawada

    IPC分类号： H01L27/10 ,  G11C11/34 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10844 ,  H01L27/10805

    摘要： The semiconductor memory device of the present invention is formed on an integrated substrate and is immune to alpha radiation. The device includes a semiconductor substrate of a first conductive type and a memory cell formed in the substrate which has a switching MOS transistor having at least a first impurity region of a second conductive type and a capacitor connected to the transistor for storing memory data. A second impurity region of the first conductive type and having a higher concentration than that of the substrate is provided on the substrate surface at a position covering the first impurity region.

    摘要翻译： 本发明的半导体存储器件形成在集成的衬底上并且不受α辐射的影响。 该器件包括第一导电类型的半导体衬底和形成在衬底中的存储单元，该存储单元具有至少具有第二导电类型的第一杂质区域的开关MOS晶体管和连接到用于存储存储器数据的晶体管的电容器。 在覆盖第一杂质区域的位置处，在基板表面上设置第一导电类型的第二杂质区域并且具有比基板更高的浓度。

    Method for fabricating a semiconductor device
    5.
    发明授权
    Method for fabricating a semiconductor device 失效
    半导体器件的制造方法

    公开(公告)号：US4410375A

    公开(公告)日：1983-10-18

    申请号：US307875

    申请日：1981-10-02

    申请人： Shizuo Sawada ,  Hiroshi Iwai ,  Satoshi Maeda

    发明人： Shizuo Sawada ,  Hiroshi Iwai ,  Satoshi Maeda

    IPC分类号： H01L27/10 ,  H01L21/225 ,  H01L21/3105 ,  H01L21/322 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78

    CPC分类号： H01L29/78 ,  H01L21/2255 ,  H01L21/3105 ,  H01L27/10805

    摘要： A method for fabricating a semiconductor device is disclosed which includes a step of forming contact holes in insulating films on a substrate, forming a silicate glass layer containing an impurity over the entire surface, and performing the phosphorus getter treatment using POCl.sub.3 at a high temperature. Even when the phosphorus getter treatment is performed after the formation of the contact holes, the substrate or electrodes exposed through the contact holes may not be reduced in thickness or damaged. The impurity may be diffused into the substrate from the silicate glass layer through the contact holes.

    摘要翻译： 公开了一种制造半导体器件的方法，其包括在基片上形成绝缘膜中的接触孔的步骤，在整个表面上形成含有杂质的硅酸盐玻璃层，并在高温下使用POCl 3进行磷吸气剂处理。 即使在形成接触孔之后进行磷吸气剂处理，也可能不会使通过接触孔露出的基板或电极的厚度减小或损坏。 杂质可以从硅酸盐玻璃层通过接触孔扩散到衬底中。

    Semiconductor memory device with stacked capacitor structure and the manufacturing method thereof
    6.
    发明授权
    Semiconductor memory device with stacked capacitor structure and the manufacturing method thereof 失效
    具有堆叠电容器结构的半导体存储器件及其制造方法

    公开(公告)号：US4951175A

    公开(公告)日：1990-08-21

    申请号：US353765

    申请日：1989-05-18

    申请人： Kei Kurosawa ,  Hidehiro Watanabe ,  Shizuo Sawada

    发明人： Kei Kurosawa ,  Hidehiro Watanabe ,  Shizuo Sawada

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10808 ,  H01L27/10835

    摘要： A dynamic random access memory with a stacked capacitor cell structure is disclosed which has a memory cell provided on a silicon substrate and having a MOSFET and a capacitor. An insulative layer is formed on the substrate, and a first polycrystalline silicon layer is formed on this insulative layer. These layers are simultaneously subjected to etching and define a contact hole which penetrates them to come in contact with the surface of the source. A second polycrystalline silicon layer is formed on the first polycrystalline silicon layer to uniformly cover the inner wall of the contact hole and that surface portion of the source which is exposed through the contact hole. The first and second silicon layers are simultaneously subjected to patterning to provide the lower electrode of the capacitor. After a capacitor insulation layer is formed on the second polycrystalline silicon layer, a third polycrystalline silicon layer is formed on the capacitor insulation layer so as to bury a recess of the second polycrystalline silicon layer. The third silicon layer constitutes the upper electrode of the capacitor.

    摘要翻译： 公开了一种具有层叠电容器单元结构的动态随机存取存储器，其具有设置在硅衬底上并具有MOSFET和电容器的存储单元。 在基板上形成绝缘层，在该绝缘层上形成第一多晶硅层。 这些层同时进行蚀刻并限定穿透它们的接触孔以与源的表面接触。 在第一多晶硅层上形成第二多晶硅层，以均匀地覆盖接触孔的内壁和通过接触孔露出的源的表面部分。 第一和第二硅层同时进行图案化以提供电容器的下电极。 在第二多晶硅层上形成电容器绝缘层之后，在电容器绝缘层上形成第三多晶硅层，从而埋入第二多晶硅层的凹部。 第三硅层构成电容器的上电极。

    Semiconductor memory device having a bit line constituted by a semiconductor layer
    9.
    发明授权
    Semiconductor memory device having a bit line constituted by a semiconductor layer 失效
    具有由半导体层构成的位线的半导体存储器件

    公开(公告)号：US5276343A

    公开(公告)日：1994-01-04

    申请号：US943144

    申请日：1992-09-10

    申请人： Jumpei Kumagai ,  Shizuo Sawada

    发明人： Jumpei Kumagai ,  Shizuo Sawada

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/78

    CPC分类号： H01L27/10864 ,  H01L27/10823 ,  H01L27/10841

    摘要： A DRAM cell having a bit line constituted by a semiconductor layer. The DRAM cell comprises a semiconductor substrate of a first conductivity type having a main surface, an insulating film formed on the main surface, an opening formed in the insulating film to communicate with the substrate, and a bit line formed by a semiconductor layer of a second conductivity type formed on the insulating film and that portion of the substrate which is exposed through the opening.

    摘要翻译： 具有由半导体层构成的位线的DRAM单元。 DRAM单元包括具有主表面的第一导电类型的半导体衬底，在主表面上形成的绝缘膜，形成在绝缘膜中的与衬底连通的开口，以及由衬底的半导体层形成的位线 形成在绝缘膜上的第二导电类型和通过开口露出的基板的那部分。

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5194752A

    公开(公告)日：1993-03-16

    申请号：US813049

    申请日：1991-12-23

    申请人： Jumpei Kumagai ,  Shizuo Sawada

    发明人： Jumpei Kumagai ,  Shizuo Sawada

    IPC分类号： G11C11/4097 ,  H01L27/108

    CPC分类号： G11C11/4097 ,  H01L27/10808

    摘要： For increasing pattern density of cell regions in a semiconductor memory device including an array of dynamic memory cells, the cell regions for cell transistor pairs are provided in a semiconductor substrate so as to be crossed by one desired bit line and two word lines adjacent thereto, and the patterns of cell regions have a same direction. Contacts for electrically connecting each bit line to common regions of cell transistor pairs are provided on respective bit lines every desired pitch at positions where each bit line intersects with cell regions. These contacts of adjacent bit lines are successively shifted in a bit line direction by approximately 1/2.sup.n pitch (n is natural numbers greater than or equal to 2).

    摘要翻译： 为了增加包括动态存储单元阵列的半导体存储器件中的单元区域的图案密度，单元晶体管对的单元区域设置在半导体衬底中，以便与一个所需的位线和与其相邻的两个字线交叉， 并且单元区域的图案具有相同的方向。 用于将每个位线电连接到单元晶体管对的公共区域的触点在每个位线与单元区域相交的位置处以每个期望的间距提供在相应的位线上。 相邻位线的这些触点在位线方向依次移位约1 / 2n间距（n为大于或等于2的自然数）。