公开(公告)号：US5956281A

公开(公告)日：1999-09-21

申请号：US39270

申请日：1998-03-16

申请人： Jun Nakai ,  Masanori Hayashikoshi

发明人： Jun Nakai ,  Masanori Hayashikoshi

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C11/401 ,  G11C11/403 ,  G11C11/408 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C29/028 ,  G11C29/50 ,  G11C29/50012 ,  G11C5/143 ,  G11C5/146 ,  G11C11/401 ,  G11C2029/5004

摘要： A switching circuit is provided which activates a shallow level detector and inactivates a deep level detector when a disturb test signal or a self refresh signal is activated. Accordingly, a shallow substrate voltage at the same level as a detection level of the shallow level detector can be generated by a substrate voltage generating circuit not only in a disturb test mode but also in a self refresh mode. As a result, the area penalty due to the shallow level detector is reduced.

摘要翻译： 提供了一种切换电路，其在干扰测试信号或自刷新信号被激活时激活浅电平检测器并使深电平检测器失活。 因此，不仅在干扰测试模式下而且在自刷新模式下，通过衬底电压发生电路可以产生与浅电平检测器的检测电平相同水平的浅衬底电压。 结果，由于浅层检测器引起的区域损失降低。

公开(公告)号：US08508986B2

公开(公告)日：2013-08-13

申请号：US13188924

申请日：2011-07-22

申请人： Hiroaki Tanizaki ,  Yasumitsu Murai ,  Takaharu Tsuji ,  Masanori Hayashikoshi

发明人： Hiroaki Tanizaki ,  Yasumitsu Murai ,  Takaharu Tsuji ,  Masanori Hayashikoshi

IPC分类号： G11C11/00

CPC分类号： G11C8/12 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675

摘要： A semiconductor device having first and second digit line drivers and a bit line driver. When the address of one segment has been input from the outside, a segment decoder selects one segment corresponding to the address and couples the same to the selected first digit line driver. When the addresses of two or more segments have been input from the outside, the segment decoder selects two or more segments corresponding to the addresses and couples the selected two or more segments to the respective digital line drivers.

摘要翻译： 一种具有第一和第二数字线驱动器和位线驱动器的半导体器件。 当从外部输入一个段的地址时，段解码器选择与地址相对应的一个段，并将其与所选择的第一位数字线驱动器相连。 当从外部输入两个或更多个段的地址时，段解码器选择对应于地址的两个或多个段，并将所选择的两个或多个段耦合到相应的数字线路驱动器。

公开(公告)号：US6088819A

公开(公告)日：2000-07-11

申请号：US910221

申请日：1997-08-13

申请人： Yukinobu Adachi ,  Hiromi Okimoto ,  Masanori Hayashikoshi

发明人： Yukinobu Adachi ,  Hiromi Okimoto ,  Masanori Hayashikoshi

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G11C11/401 ,  G11C11/407 ,  G11C29/14 ,  G11C29/50 ,  H01L21/822 ,  H01L27/04 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/50 ,  G11C11/401

摘要： In a DRAM, a boosted voltage Vpp is applied to a selected word line WL1 in a normal mode. In a test mode, a power supply voltage Vcc at a level lower than Vpp level is applied onto selected word line WL1. High data written into memory cell in the test mode of the DRAM is at the level lower than that of the high data written into memory cell in the normal mode. Therefore, a time before an H.fwdarw.L error occurs can be reduced, and a test time can be reduced.

摘要翻译： 在DRAM中，升压电压Vpp以正常模式施加到所选字线WL1。 在测试模式中，将低于Vpp电平的电源电压Vcc施加到所选字线WL1上。 在DRAM的测试模式下写入存储单元的高数据处于正常模式下写入存储单元的高数据的数据级。 因此，可以减少发生H-> L误差之前的时间，并且可以减少测试时间。

公开(公告)号：US6011428A

公开(公告)日：2000-01-04

申请号：US135650

申请日：1993-10-14

申请人： Masaki Tsukude ,  Masanori Hayashikoshi

发明人： Masaki Tsukude ,  Masanori Hayashikoshi

IPC分类号： G05F1/56 ,  G05F3/24 ,  G11C5/14 ,  G11C11/401 ,  G11C11/407 ,  H03K5/003 ,  G05F1/10

CPC分类号： G05F3/245 ,  G05F3/24 ,  G11C5/147 ,  Y10S323/907

摘要： The level shifter circuit of an internal down converter includes a P channel MOS transistor constituting a resistance component, and a resistor constituting a resistance component. The temperature coefficient of resistance component is set larger than the temperature coefficient of resistance component so that the output voltage of level shifter circuit has a negative temperature characteristic. If a reference voltage generated by reference voltage generation circuit decreases when operating at a high temperature, the output voltage of level shifter circuit decreases as well. Thus, change in an internal voltage due to change in the operation temperature can be compensated.

摘要翻译： 内部下变频器的电平移位电路包括构成电阻分量的P沟道MOS晶体管和构成电阻分量的电阻。 电阻分量的温度系数设定为大于电阻分量的温度系数，使得电平移位器电路的输出电压具有负温度特性。 如果在高温工作时由参考电压产生电路产生的参考电压降低，则电平转换器电路的输出电压也会降低。 因此，可以补偿由于操作温度的变化引起的内部电压的变化。

公开(公告)号：US5465063A

公开(公告)日：1995-11-07

申请号：US49398

申请日：1993-04-21

申请人： Tatsuya Fukuda ,  Shigeru Mori ,  Masanori Hayashikoshi ,  Seiji Sawada

发明人： Tatsuya Fukuda ,  Shigeru Mori ,  Masanori Hayashikoshi ,  Seiji Sawada

IPC分类号： G11C5/14 ,  G11C7/22 ,  G11C11/406 ,  H03K3/03 ,  H03K3/354 ,  H03L1/02

CPC分类号： G11C11/40626 ,  G11C11/406 ,  G11C5/147 ,  G11C7/22 ,  H03K3/0315

摘要： A pulse signal generating circuit includes a ring oscillator and an internal voltage generating circuit. The internal voltage generating circuit generates an internal voltage depending on an operation temperature. The internal voltage is low at a normal temperature, and is high at a high temperature. Each inverter in the ring oscillator is driven by the internal voltage supplied from the internal voltage generating circuit. Thereby, a period of a pulse signal increases at a normal temperature, and decreases at a high temperature.

摘要翻译： 脉冲信号发生电路包括环形振荡器和内部电压产生电路。 内部电压产生电路根据操作温度产生内部电压。 内部电压在正常温度下为低电平，在高温下为高电平。 环形振荡器中的每个反相器由内部电压产生电路提供的内部电压驱动。 因此，脉冲信号的周期在正常温度下增加，并且在高温下降低。

公开(公告)号：US5315548A

公开(公告)日：1994-05-24

申请号：US900368

申请日：1992-06-18

申请人： Tsukasa Ooishi ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi ,  Shinji Kawai ,  Mikio Asakura ,  Masaki Tsukude ,  Katsuhiro Suma ,  Shigeki Tomishima ,  Kazuyasu Fujishima

发明人： Tsukasa Ooishi ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi ,  Shinji Kawai ,  Mikio Asakura ,  Masaki Tsukude ,  Katsuhiro Suma ,  Shigeki Tomishima ,  Kazuyasu Fujishima

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C8/12 ,  G11C11/401 ,  G11C11/41 ,  H01L21/8242 ,  H01L27/108 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C8/12 ,  G11C7/10

摘要： Column address A0-A11 is once predecoded by a first predecoder PD1, a second predecoder PD2, and a CDE buffer CDB and then applied to a column decoder CD. Column decoder CD selectively drives one of a plurality of column selecting lines CSL on the basis of the applied predecoded signals. This causes corresponding bit lines in respective memory cell arrays MCA1-MCA4 to be simultaneously selected. Column decoder CD includes a plurality of column drivers corresponding to the plurality of column selecting lines, and the column drivers are divided into a plurality of groups. The predecoded signals applied from second predecoder PD2 and CDE buffer CDB to column decoder CD are generated independently for respective groups, and signal lines for them are also distributed to respective groups. This causes the length of wiring of each predecoded signal line to be shortened.

摘要翻译： 列地址A0-A11由第一预解码器PD1，第二预解码器PD2和CDE缓冲器CDB预先解码，然后应用于列解码器CD。 列解码器CD基于所应用的预解码信号选择性地驱动多个列选择线CSL中的一个。 这使得相应的存储单元阵列MCA1-MCA4中的相应位线被同时选择。 列解码器CD包括对应于多个列选择线的多个列驱动器，列驱动器被分成多个组。 从第二预解码器PD2和CDE缓冲器CDB施加到列解码器CD的预解码信号针对各个组独立地生成，并且它们的信号线也被分配给各个组。 这导致每个预解码信号线的布线长度被缩短。

公开(公告)号：US20120075921A1

公开(公告)日：2012-03-29

申请号：US13188924

申请日：2011-07-22

申请人： Hiroaki Tanizaki ,  Yasumitsu Murai ,  Takaharu Tsuji ,  Masanori Hayashikoshi

发明人： Hiroaki Tanizaki ,  Yasumitsu Murai ,  Takaharu Tsuji ,  Masanori Hayashikoshi

IPC分类号： G11C11/02

CPC分类号： G11C8/12 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675

摘要： A semiconductor device using a segment writing method capable of achieving a normal write operation is provided. The first DL driver and the second DL driver each cause a magnetizing current to flow through a digit line of a selected block. A BL driver causes a write current to flow in a direction corresponding to the logic of a data signal to all bit lines in a selected segment, and writes the data signal to a memory cell of the selected block. A segment decoder, when the address of one segment has been input from the outside, selects one segment corresponding to the address and couples the same to the selected first DL driver, and the segment decoder, when the addresses of two or more segments have been input from the outside, selects two or more segments corresponding to the addresses and couples the selected two or more segments to the first DL driver and the second DL driver, respectively.

摘要翻译： 提供一种使用能够实现正常写入操作的段写入方法的半导体器件。 第一DL驱动器和第二DL驱动器各自引起磁化电流流过所选块的数字线。 BL驱动器使写入电流在与所选择的段中的所有位线对应的数据信号逻辑的方向上流动，并将数据信号写入所选择的块的存储单元。 段解码器当从外部输入一个段的地址时，选择与该地址相对应的一个段，并将其与所选择的第一DL驱动器相连，并且当两个或多个段的地址已被 从外部输入，选择对应于地址的两个或更多个段，并将所选择的两个或多个段分别耦合到第一DL驱动器和第二DL驱动器。

公开(公告)号：US06483761B2

公开(公告)日：2002-11-19

申请号：US09968899

申请日：2001-10-03

申请人： Hiroshi Akamatsu ,  Masanori Hayashikoshi

发明人： Hiroshi Akamatsu ,  Masanori Hayashikoshi

IPC分类号： G11C700

CPC分类号： G11C29/14

摘要： The semiconductor memory device in accordance with the present invention allows evaluation of input/output terminal dependency of noise characteristic at the time of data output, it has a normal operation mode and a test mode, and includes a plurality of output buffers and selecting means for selectively activating at least one output buffer among the plurality of output buffers in the test mode.

公开(公告)号：USRE36089E

公开(公告)日：1999-02-09

申请号：US652008

申请日：1996-05-23

申请人： Tsukasa Ooishi ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi ,  Shinji Kawai ,  Mikio Asakura ,  Masaki Tsukude ,  Katsuhiro Suma ,  Shigeki Tomishima ,  Kazuyasu Fujishima

发明人： Tsukasa Ooishi ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi ,  Shinji Kawai ,  Mikio Asakura ,  Masaki Tsukude ,  Katsuhiro Suma ,  Shigeki Tomishima ,  Kazuyasu Fujishima

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C8/12 ,  G11C11/401 ,  G11C11/41 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C8/12 ,  G11C7/10

摘要： Column address A0-A11 is once predecoded by a first predecoder PD1, a second predecoder PD2, and a CDE buffer CDB and then applied to a column decoder CD. Column decoder CD selectively drives one of a plurality of column selecting lines CSL on the basis of the applied predecoded signals. This causes corresponding bit lines in respective memory cell arrays MCA1-MCA4 to be simultaneously selected. Column decoder CD includes a plurality of column drivers corresponding to the plurality of column selecting lines, and the column drivers are divided into a plurality of groups. The predecoded signals applied from second predecoder PD2 and CDE buffer CDB to column decoder CD are generated independently for respective groups, and signal lines for them are also distributed to respective groups. This causes the length of wiring of each predecoded signal line to be shortened.

摘要翻译： 列地址A0-A11由第一预解码器PD1，第二预解码器PD2和CDE缓冲器CDB预先解码，然后应用于列解码器CD。 列解码器CD基于所应用的预解码信号选择性地驱动多个列选择线CSL中的一个。 这使得相应的存储单元阵列MCA1-MCA4中的相应位线被同时选择。 列解码器CD包括对应于多个列选择线的多个列驱动器，列驱动器被分成多个组。 从第二预解码器PD2和CDE缓冲器CDB施加到列解码器CD的预解码信号针对各个组独立地生成，并且它们的信号线也被分配给各个组。 这导致每个预解码信号线的布线长度被缩短。

公开(公告)号：US5617362A

公开(公告)日：1997-04-01

申请号：US629682

申请日：1996-04-09

申请人： Shigeru Mori ,  Tomio Suzuki ,  Masanori Hayashikoshi

发明人： Shigeru Mori ,  Tomio Suzuki ,  Masanori Hayashikoshi

IPC分类号： G11C11/417 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C11/4093 ,  G11C11/4096 ,  G11C7/00

CPC分类号： G11C7/1057 ,  G11C11/4093 ,  G11C11/4096 ,  G11C7/1024 ,  G11C7/1051 ,  G11C7/106

摘要： A DRAM includes an output terminal, a memory cell array having a plurality of memory cells, a row decoder, a column decoder, an input/output circuit, a data extending circuit, an output buffer circuit, and a control circuit. The data extending circuit extends each data read out from the input/output circuit until a subsequent data is read out. The output buffer circuit responds to the extended data from the data extending circuit for providing output data sequentially to the output terminal. In response to an output control signal provided from the control circuit, the output terminal is set to a high impedance state before each output data is provided from the output buffer circuit.

摘要翻译： DRAM包括输出端子，具有多个存储单元的存储单元阵列，行解码器，列解码器，输入/输出电路，数据扩展电路，输出缓冲电路和控制电路。 数据扩展电路扩展从输入/输出电路读出的每个数据，直到读出后续数据。 输出缓冲器电路响应来自数据扩展电路的扩展数据，以将输出数据顺序地提供给输出端。 响应于从控制电路提供的输出控制信号，在从输出缓冲器电路提供每个输出数据之前，将输出端子设置为高阻抗状态。