公开(公告)号：US6011428A

公开(公告)日：2000-01-04

申请号：US135650

申请日：1993-10-14

申请人： Masaki Tsukude ,  Masanori Hayashikoshi

发明人： Masaki Tsukude ,  Masanori Hayashikoshi

IPC分类号： G05F1/56 ,  G05F3/24 ,  G11C5/14 ,  G11C11/401 ,  G11C11/407 ,  H03K5/003 ,  G05F1/10

CPC分类号： G05F3/245 ,  G05F3/24 ,  G11C5/147 ,  Y10S323/907

摘要： The level shifter circuit of an internal down converter includes a P channel MOS transistor constituting a resistance component, and a resistor constituting a resistance component. The temperature coefficient of resistance component is set larger than the temperature coefficient of resistance component so that the output voltage of level shifter circuit has a negative temperature characteristic. If a reference voltage generated by reference voltage generation circuit decreases when operating at a high temperature, the output voltage of level shifter circuit decreases as well. Thus, change in an internal voltage due to change in the operation temperature can be compensated.

摘要翻译： 内部下变频器的电平移位电路包括构成电阻分量的P沟道MOS晶体管和构成电阻分量的电阻。 电阻分量的温度系数设定为大于电阻分量的温度系数，使得电平移位器电路的输出电压具有负温度特性。 如果在高温工作时由参考电压产生电路产生的参考电压降低，则电平转换器电路的输出电压也会降低。 因此，可以补偿由于操作温度的变化引起的内部电压的变化。

公开(公告)号：US5315548A

公开(公告)日：1994-05-24

申请号：US900368

申请日：1992-06-18

申请人： Tsukasa Ooishi ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi ,  Shinji Kawai ,  Mikio Asakura ,  Masaki Tsukude ,  Katsuhiro Suma ,  Shigeki Tomishima ,  Kazuyasu Fujishima

发明人： Tsukasa Ooishi ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi ,  Shinji Kawai ,  Mikio Asakura ,  Masaki Tsukude ,  Katsuhiro Suma ,  Shigeki Tomishima ,  Kazuyasu Fujishima

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C8/12 ,  G11C11/401 ,  G11C11/41 ,  H01L21/8242 ,  H01L27/108 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C8/12 ,  G11C7/10

摘要： Column address A0-A11 is once predecoded by a first predecoder PD1, a second predecoder PD2, and a CDE buffer CDB and then applied to a column decoder CD. Column decoder CD selectively drives one of a plurality of column selecting lines CSL on the basis of the applied predecoded signals. This causes corresponding bit lines in respective memory cell arrays MCA1-MCA4 to be simultaneously selected. Column decoder CD includes a plurality of column drivers corresponding to the plurality of column selecting lines, and the column drivers are divided into a plurality of groups. The predecoded signals applied from second predecoder PD2 and CDE buffer CDB to column decoder CD are generated independently for respective groups, and signal lines for them are also distributed to respective groups. This causes the length of wiring of each predecoded signal line to be shortened.

摘要翻译： 列地址A0-A11由第一预解码器PD1，第二预解码器PD2和CDE缓冲器CDB预先解码，然后应用于列解码器CD。 列解码器CD基于所应用的预解码信号选择性地驱动多个列选择线CSL中的一个。 这使得相应的存储单元阵列MCA1-MCA4中的相应位线被同时选择。 列解码器CD包括对应于多个列选择线的多个列驱动器，列驱动器被分成多个组。 从第二预解码器PD2和CDE缓冲器CDB施加到列解码器CD的预解码信号针对各个组独立地生成，并且它们的信号线也被分配给各个组。 这导致每个预解码信号线的布线长度被缩短。

公开(公告)号：US6097180A

公开(公告)日：2000-08-01

申请号：US353360

申请日：1999-07-15

申请人： Masaki Tsukude ,  Masanori Hayashikoshi

发明人： Masaki Tsukude ,  Masanori Hayashikoshi

IPC分类号： G05F1/56 ,  G05F3/24 ,  G11C5/14 ,  G11C11/401 ,  G11C11/407 ,  H03K5/003 ,  G05F3/16 ,  G05F1/10

CPC分类号： G05F3/245 ,  G05F3/24 ,  G11C5/147 ,  Y10S323/907

摘要： The level shifter circuit of an internal down converter includes a P channel MOS transistor constituting a resistance component, and a resistor constituting a resistance component. The temperature coefficient of resistance component is set larger than the temperature coefficient of resistance component so that the output voltage of level shifter circuit has a negative temperature characteristic. If a reference voltage generated by reference voltage generation circuit decreases when operating at a high temperature, the output voltage of level shifter circuit decreases as well. Thus, change in an internal voltage due to change in the operation temperature can be compensated.

公开(公告)号：USRE36089E

公开(公告)日：1999-02-09

申请号：US652008

申请日：1996-05-23

申请人： Tsukasa Ooishi ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi ,  Shinji Kawai ,  Mikio Asakura ,  Masaki Tsukude ,  Katsuhiro Suma ,  Shigeki Tomishima ,  Kazuyasu Fujishima

发明人： Tsukasa Ooishi ,  Kazutami Arimoto ,  Hideto Hidaka ,  Masanori Hayashikoshi ,  Shinji Kawai ,  Mikio Asakura ,  Masaki Tsukude ,  Katsuhiro Suma ,  Shigeki Tomishima ,  Kazuyasu Fujishima

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C8/12 ,  G11C11/401 ,  G11C11/41 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

CPC分类号： G11C8/12 ,  G11C7/10

摘要： Column address A0-A11 is once predecoded by a first predecoder PD1, a second predecoder PD2, and a CDE buffer CDB and then applied to a column decoder CD. Column decoder CD selectively drives one of a plurality of column selecting lines CSL on the basis of the applied predecoded signals. This causes corresponding bit lines in respective memory cell arrays MCA1-MCA4 to be simultaneously selected. Column decoder CD includes a plurality of column drivers corresponding to the plurality of column selecting lines, and the column drivers are divided into a plurality of groups. The predecoded signals applied from second predecoder PD2 and CDE buffer CDB to column decoder CD are generated independently for respective groups, and signal lines for them are also distributed to respective groups. This causes the length of wiring of each predecoded signal line to be shortened.

摘要翻译： 列地址A0-A11由第一预解码器PD1，第二预解码器PD2和CDE缓冲器CDB预先解码，然后应用于列解码器CD。 列解码器CD基于所应用的预解码信号选择性地驱动多个列选择线CSL中的一个。 这使得相应的存储单元阵列MCA1-MCA4中的相应位线被同时选择。 列解码器CD包括对应于多个列选择线的多个列驱动器，列驱动器被分成多个组。 从第二预解码器PD2和CDE缓冲器CDB施加到列解码器CD的预解码信号针对各个组独立地生成，并且它们的信号线也被分配给各个组。 这导致每个预解码信号线的布线长度被缩短。

公开(公告)号：US5249155A

公开(公告)日：1993-09-28

申请号：US819208

申请日：1992-01-10

申请人： Kazutami Arimoto ,  Hideto Hidaka ,  Mikio Asakura ,  Masanori Hayashikoshi ,  Masaki Tsukude ,  Shinji Kawai ,  Tsukasa Ooishi

发明人： Kazutami Arimoto ,  Hideto Hidaka ,  Mikio Asakura ,  Masanori Hayashikoshi ,  Masaki Tsukude ,  Shinji Kawai ,  Tsukasa Ooishi

IPC分类号： H01L21/8234 ,  G05F1/46 ,  G11C5/14 ,  G11C11/401 ,  G11C11/403 ,  G11C11/407 ,  G11C11/409 ,  H01L21/822 ,  H01L21/8244 ,  H01L27/04 ,  H01L27/06 ,  H01L27/10 ,  H01L27/11 ,  H03K17/30

CPC分类号： H03K17/302 ,  G05F1/465 ,  G11C5/147 ,  H01L2924/0002

摘要： An n channel driver circuit comprised of an N channel MOS transistor is provided in parallel to a driver circuit comprised of a P channel MOS transistor. Normally, n channel driver circuit supplies an internal supply voltage, to activate driver circuit only at the time of current peak. Thus, an insufficient capability of n.sup.- channel driver circuit to supply current is supplemented.

摘要翻译： 由N沟道MOS晶体管构成的n沟道驱动电路与由P沟道MOS晶体管构成的驱动电路并联设置。 通常，n通道驱动电路提供内部电源电压，仅在当前峰值时激活驱动电路。 因此，补充了n沟道驱动电路不足以提供电流的能力。

公开(公告)号：US06707735B2

公开(公告)日：2004-03-16

申请号：US10120445

申请日：2002-04-12

申请人： Ryu Makabe ,  Masaki Tsukude ,  Hirotoshi Sato

发明人： Ryu Makabe ,  Masaki Tsukude ,  Hirotoshi Sato

IPC分类号： G11C700

CPC分类号： G11C29/46

摘要： When address signal bits and/or data bits in a predetermined pattern are accessed a predetermined number of times successively, a test mode can be set. By using address signal bits and/or data bits as a test command for designating a test content, a test content is specified. A semiconductor memory device with an interface compatible with an interface of a normal static random access memory is provided.

摘要翻译： 当预定模式的地址信号位和/或数据位连续访问预定次数时，可以设置测试模式。 通过使用地址信号位和/或数据位作为用于指定测试内容的测试命令，指定测试内容。 提供具有与普通静态随机存取存储器的接口兼容的接口的半导体存储器件。

公开(公告)号：US06590823B2

公开(公告)日：2003-07-08

申请号：US09988172

申请日：2001-11-19

申请人： Masaki Tsukude

发明人： Masaki Tsukude

IPC分类号： G11C700

CPC分类号： G11C11/406

摘要： A refresh circuit performs directive operation for the execution of refresh operation in response to a cycle signal cyclically output from a timer circuit provided in a command-signal activating circuit. To execute testing, a stop signal generated in response to an external signal is activated, the activated stop signal is input to an AND gate, and the cycle signal is thereby invalidated. This causes the refresh operation to terminate, thereby enabling this semiconductor memory device to refresh characteristic testing to be performed.

公开(公告)号：US06556485B2

公开(公告)日：2003-04-29

申请号：US09972242

申请日：2001-10-09

申请人： Tadayuki Shimizu ,  Hirotoshi Sato ,  Masaki Tsukude

发明人： Tadayuki Shimizu ,  Hirotoshi Sato ,  Masaki Tsukude

IPC分类号： G11C700

CPC分类号： G11C7/1051

摘要： An output buffer includes first current driving units connected in parallel between a power-supply voltage and an output node; second current driving units connected in parallel between a ground voltage and an output node; a plurality of operation selection circuits setting the respective first and second current driving units to be in either activated or inactivated state in a non-volatile manner; first signal transmission circuits arranged respectively corresponding to the first current driving circuits and each transmitting the level of output data with a similar first propagation time period; and second signal transmission circuits arranged respectively corresponding to the second current driving units and each transmitting the level of the output data with a similar second propagation time period.

公开(公告)号：US06341098B2

公开(公告)日：2002-01-22

申请号：US09846223

申请日：2001-05-02

申请人： Tadato Yamagata ,  Kazutami Arimoto ,  Masaki Tsukude

发明人： Tadato Yamagata ,  Kazutami Arimoto ,  Masaki Tsukude

IPC分类号： G11C700

CPC分类号： G11C5/14 ,  G11C5/147 ,  G11C7/22 ,  G11C8/08 ,  G11C11/4074 ,  H03K19/0016

摘要： A variable impedance power supply line and a variable impedance ground line supplying voltages VCL1 and VSL1, respectively, are set to a low impedance state in a stand-by cycle and in a row related signal set period, and to a high impedance state in a column circuitry valid time period. Variable impedance power supply line and variable impedance ground line supplying voltages VCL2 and VSL2, respectively, are set to a high impedance state in the stand-by cycle, and low impedance state in the active cycle and in the row related signal reset time period. Inverters operate as operating power supply voltage of voltages VCL1 and VSL2 or voltages VCL2 and VSL1, in accordance with a logic level of an output signal in the stand-by cycle and in the active cycle. Thus a semiconductor memory device is provided in which subthreshold current in the stand-by cycle and active DC current in the active cycle can be reduced.

摘要翻译： 分别提供电压VCL1和VSL1的可变阻抗电源线和可变阻抗接地线在待机周期和行相关信号设定周期中被设置为低阻抗状态，并且在 列电路有效时间段。 可变阻抗电源线和可变阻抗地线供电电压VCL2和VSL2分别在待机周期中被设置为高阻抗状态，并且在有效周期和行相关信号复位时间段中被设置为低阻抗状态。 根据待机周期和激活周期中的输出信号的逻辑电平，变频器作为电压VCL1和VSL2的工作电源电压或电压VCL2和VSL1运行。 因此，提供半导体存储器件，其中可以减少备用循环中的次阈值电流和有效周期中的有效直流电流。

公开(公告)号：US6150728A

公开(公告)日：2000-11-21

申请号：US854754

申请日：1997-05-12

申请人： Masaki Tsukude ,  Kazutami Arimoto

发明人： Masaki Tsukude ,  Kazutami Arimoto

IPC分类号： G11C11/401 ,  H01L21/321 ,  H01L21/60 ,  H01L21/8242 ,  H01L23/495 ,  H01L23/50 ,  H01L27/105 ,  H01L27/108 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/06 ,  H01L23/4951 ,  H01L23/50 ,  H01L27/105 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01024 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01082

摘要： On a surface of a semiconductor chip having a longer side and a shorter side, a line of a plurality of first pads and a line of a plurality of second pads are arranged in the shape of a cross. Upon multibit expansion, increase in length of the longer side of semiconductor chip can be suppressed even though the number of pads is increased by additionally providing the second pad. In addition, there is no need to reduce the pitch between pads. Thus, a semiconductor memory device allowing multibit expansion is provided without an increase in size of the chip and the pad or reduction in pitches between pads and between pins.

摘要翻译： 在具有长边和短边的半导体芯片的表面上，多个第一焊盘的线和多个第二焊盘的线以交叉的形式布置。 在多位扩展时，即使通过另外设置第二焊盘来增加焊盘的数量，也可以抑制半导体芯片的长边的长度的增加。 此外，不需要减小垫之间的间距。 因此，提供了允许多位扩展的半导体存储器件，而不增加芯片和焊盘的尺寸，或者减小焊盘之间和引脚之间的间距。