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    SEMICONDUCTOR MEMORY DEVICE HAVING IMPROVED REFRESH CHARACTERISTICS
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE HAVING IMPROVED REFRESH CHARACTERISTICS 有权
    具有改进的刷新特性的半导体存储器件

    公开(公告)号：US20130016574A1

    公开(公告)日：2013-01-17

    申请号：US13548484

    申请日：2012-07-13

    申请人： Jung-sik Kim ,  Cheol Kim ,  Sang-ho Shin ,  Jung-bae Lee ,  Chan-yong Lee ,  Sung-min Yim ,  Tae-seong Jang ,  Joo-sun Choi

    发明人： Jung-sik Kim ,  Cheol Kim ,  Sang-ho Shin ,  Jung-bae Lee ,  Chan-yong Lee ,  Sung-min Yim ,  Tae-seong Jang ,  Joo-sun Choi

    IPC分类号： G11C29/08 ,  G11C7/00

    CPC分类号： G11C29/50016 ,  G11C5/04 ,  G11C11/40 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622 ,  G11C2211/4061 ,  G11C2211/4065

    摘要： A semiconductor memory device having improved refresh characteristics includes a memory array including a plurality of memory cells; a test unit configured to test refresh characteristics of the memory array and generate a first fail address signal; a storage unit configured to store the first fail address signal; and a refresh unit configured to perform a refresh operation on the memory array, wherein the refresh unit is configured to receive the first fail address signal from the storage unit, perform the refresh operation on a first memory cell that does not correspond to the first fail address signal according to a first period, and perform the refresh operation on a second memory cell that corresponds to the first fail address signal according to a second period that is shorter than the first period.

    摘要翻译： 具有改进的刷新特性的半导体存储器件包括包括多个存储器单元的存储器阵列; 测试单元，被配置为测试所述存储器阵列的刷新特性并产生第一故障地址信号; 存储单元，被配置为存储所述第一失败地址信号; 以及刷新单元，被配置为对所述存储器阵列执行刷新操作，其中所述刷新单元被配置为从所述存储单元接收所述第一故障地址信号，对与所述第一故障不对应的第一存储器单元执行刷新操作 根据第一期间的地址信号，根据比第一期间短的第二期间对与第一失败地址信号对应的第二存储单元进行刷新动作。

    Semiconductor memory device having improved refresh characteristics
    3.
    发明授权
    Semiconductor memory device having improved refresh characteristics 有权
    具有改善的刷新特性的半导体存储器件

    公开(公告)号：US09036439B2

    公开(公告)日：2015-05-19

    申请号：US13548484

    申请日：2012-07-13

    申请人： Jung-sik Kim ,  Cheol Kim ,  Sang-ho Shin ,  Jung-bae Lee ,  Chan-yong Lee ,  Sung-min Yim ,  Tae-seong Jang ,  Joo-sun Choi

    发明人： Jung-sik Kim ,  Cheol Kim ,  Sang-ho Shin ,  Jung-bae Lee ,  Chan-yong Lee ,  Sung-min Yim ,  Tae-seong Jang ,  Joo-sun Choi

    IPC分类号： G11C29/08 ,  G11C7/00 ,  G11C29/50 ,  G11C11/406 ,  G11C5/04 ,  G11C11/40

    CPC分类号： G11C29/50016 ,  G11C5/04 ,  G11C11/40 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/40622 ,  G11C2211/4061 ,  G11C2211/4065

    摘要： A semiconductor memory device having improved refresh characteristics includes a memory array including a plurality of memory cells; a test unit configured to test refresh characteristics of the memory array and generate a first fail address signal; a storage unit configured to store the first fail address signal; and a refresh unit configured to perform a refresh operation on the memory array, wherein the refresh unit is configured to receive the first fail address signal from the storage unit, perform the refresh operation on a first memory cell that does not correspond to the first fail address signal according to a first period, and perform the refresh operation on a second memory cell that corresponds to the first fail address signal according to a second period that is shorter than the first period.

    摘要翻译： 具有改进的刷新特性的半导体存储器件包括包括多个存储器单元的存储器阵列; 测试单元，被配置为测试所述存储器阵列的刷新特性并产生第一故障地址信号; 存储单元，被配置为存储所述第一失败地址信号; 以及刷新单元，被配置为对所述存储器阵列执行刷新操作，其中所述刷新单元被配置为从所述存储单元接收所述第一故障地址信号，对与所述第一故障不对应的第一存储器单元执行刷新操作 根据第一期间的地址信号，根据比第一期间短的第二期间对与第一失败地址信号对应的第二存储单元进行刷新动作。

    SEMICONDUCTOR MEMORY DEVICE THAT CONTROLS REFRESH PERIOD, MEMORY SYSTEM AND OPERATING METHOD THEREOF
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE THAT CONTROLS REFRESH PERIOD, MEMORY SYSTEM AND OPERATING METHOD THEREOF 有权
    控制刷新周期，存储器系统及其操作方法的半导体存储器件

    公开(公告)号：US20140016422A1

    公开(公告)日：2014-01-16

    申请号：US13937747

    申请日：2013-07-09

    申请人： Jung-sik Kim ,  Cheol Kim ,  Sang-ho Shin

    发明人： Jung-sik Kim ,  Cheol Kim ,  Sang-ho Shin

    IPC分类号： G11C7/00

    CPC分类号： G11C11/406 ,  G11C7/00 ,  G11C11/402 ,  G11C11/40603 ,  G11C11/40622 ,  G11C11/408 ,  G11C2211/406

    摘要： A semiconductor memory device includes a cell array and a refresh controller coupled to the cell array. The refresh controller is configured to insert at least one insertion refresh address in a first refresh address sequence based on address information about the cell array to generate a second refresh address sequence and to apply the second refresh address sequence to the cell array, such that selected cells may be refreshed more frequently without increasing an overall refresh rate.

    摘要翻译： 半导体存储器件包括单元阵列和耦合到单元阵列的刷新控制器。 所述刷新控制器被配置为基于关于所述单元阵列的地址信息将第一刷新地址序列中的至少一个插入刷新地址插入以生成第二刷新地址序列，并且将所述第二刷新地址序列应用于所述单元阵列，使得所选择的 可以更频繁地刷新单元，而不增加整体刷新率。

    High-voltage generating circuit including charge transfer switching circuit for selectively controlling body bias voltage of charge transfer device
    8.
    发明申请
    High-voltage generating circuit including charge transfer switching circuit for selectively controlling body bias voltage of charge transfer device 有权
    高电压发生电路包括用于选择性地控制电荷转移装置的体偏置电压的电荷转移开关电路

    公开(公告)号：US20070286007A1

    公开(公告)日：2007-12-13

    申请号：US11709768

    申请日：2007-02-23

    申请人： Jung-sik Kim ,  Soo-man Hwang ,  Young-min Jang

    发明人： Jung-sik Kim ,  Soo-man Hwang ,  Young-min Jang

    IPC分类号： G11C5/14

    CPC分类号： G11C5/145 ,  G11C11/4074

    摘要： Provided are a charge transfer switch circuit for selectively controlling body bias voltage of a charge transfer device, and a boosted voltage generating circuit having the same. The charge transfer switch circuit may include a capacitor whose voltage is boosted based on first and second control signals, a first transistor connected between a supply voltage and the capacitor and having a gate receiving a precharge signal, a second transistor connected between a first node and a second node and having a gate connected to a terminal of the capacitor, a third transistor connected between the first node and a bulk voltage of the second transistor and having a gate receiving the first control signal, and a fourth transistor connected between the bulk voltage of the second transistor and a ground voltage and having a gate receiving the second control signal.

    摘要翻译： 提供了一种用于选择性地控制电荷转移装置的体偏置电压的电荷转移开关电路，以及具有该电荷转移开关电路的升压电压产生电路。 电荷转移开关电路可以包括基于第一和第二控制信号升压其电压的电容器，连接在电源电压和电容器之间并具有接收预充电信号的栅极的第一晶体管，连接在第一节点和 第二节点，并且具有连接到所述电容器的端子的栅极;第三晶体管，连接在所述第一节点和所述第二晶体管的体电压之间，并且具有接收所述第一控制信号的栅极，以及连接在所述体电压 的第二晶体管和接地电压，并且具有接收第二控制信号的栅极。

    Internal power generating apparatus, multichannel memory including the same, and processing system employing the multichannel memory
    10.
    发明授权
    Internal power generating apparatus, multichannel memory including the same, and processing system employing the multichannel memory 有权
    内部发电装置，包括该内部发电装置的多通道存储器，以及采用多通道存储器的处理系统

    公开(公告)号：US08315121B2

    公开(公告)日：2012-11-20

    申请号：US12900624

    申请日：2010-10-08

    申请人： Jung-sik Kim ,  Ho-cheol Lee ,  Jang-woo Ryu

    发明人： Jung-sik Kim ,  Ho-cheol Lee ,  Jang-woo Ryu

    IPC分类号： G11C5/14

    CPC分类号： G06F1/26 ,  G06F1/3225 ,  G06F1/3275 ,  G06F1/3287 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171

    摘要： An internal power generating system for a semiconductor device is disclosed. The device may include a plurality of channels. The system comprises a reference voltage generator configured to generate a reference voltage. The system further comprises a plurality of internal power generators that are allocated to the plurality of channels in one-to-one correspondence and that are configured to commonly use the reference voltage generated by the reference voltage generator. Each internal power generator may be configured to receive a fed back internal power voltage, to compare the fed back internal power voltage to the reference voltage, and to generate an internal power voltage based on the comparison. The system further comprises a plurality of channel state detectors that are allocated to the plurality of channels in one-to-one correspondence, and that are configured to respectively detect operation states of the plurality of channels based on separate respective sets of command signals for each channel. The system additional comprises a plurality of internal power controllers that are allocated to the plurality of channels in one-to-one correspondence, and that are configured to respectively control driving capabilities for the internal power voltages according to the detected operation states.

    摘要翻译： 公开了一种用于半导体器件的内部发电系统。 该设备可以包括多个信道。 该系统包括被配置为产生参考电压的参考电压发生器。 该系统还包括多个内部功率发生器，其以一一对应的方式分配给多个通道，并且被配置为共同使用由参考电压发生器产生的参考电压。 每个内部发电机可以被配置为接收反馈内部电力电压，以将反馈内部电力电压与参考电压进行比较，并且基于该比较来产生内部电力电压。 该系统还包括多个通道状态检测器，其以一一对应的方式分配给多个通道，并且被配置为分别基于各个命令信号分别检测多个通道的操作状态 渠道。 该系统附加包括一对一对应地分配给多个通道的多个内部功率控制器，并且被配置为分别根据检测到的操作状态来控制内部电源电压的驱动能力。