公开(公告)号：US08963236B2

公开(公告)日：2015-02-24

申请号：US13714396

申请日：2012-12-13

申请人： Jungwoo Song ,  Jaekyu Lee

发明人： Jungwoo Song ,  Jaekyu Lee

IPC分类号： H01L27/105 ,  H01L27/10 ,  H01L27/22 ,  H01L45/00 ,  H01L27/24 ,  H01L27/02

CPC分类号： H01L23/528 ,  H01L23/5226 ,  H01L27/0203 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2463 ,  H01L29/4236 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L2924/0002 ,  H01L2924/00

摘要： Provided are data storage devices and methods of manufacturing the same. The device may include a plurality of cell selection parts formed in a substrate, a plate conductive pattern covering the cell selection parts and electrically connected to first terminals of the cell selection parts, a plurality of through-pillars penetrating the plate conductive pattern and insulated from the plate conductive pattern, and a plurality of data storage parts directly connected to the plurality of through-pillars, respectively. The data storage parts may be electrically connected to second terminals of the cell selection parts, respectively.

摘要翻译： 提供数据存储装置及其制造方法。 该器件可以包括形成在衬底中的多个电池选择部件，覆盖电池选择部分并电连接到电池选择部件的第一端子的板状导电图案，穿过板状导电图案并与之绝缘的多个贯通柱 板状导电图案，以及分别与多个贯通柱直接连接的多个数据存储部。 数据存储部分可以分别电连接到小区选择部分的第二终端。

公开(公告)号：US11099803B2

公开(公告)日：2021-08-24

申请号：US16426702

申请日：2019-05-30

申请人： Jaekyu Lee ,  Jaelark Jung ,  Jaeyong Jang

发明人： Jaekyu Lee ,  Jaelark Jung ,  Jaeyong Jang

IPC分类号： G06F3/147 ,  G06Q30/02 ,  G09G3/20 ,  G06F1/3215 ,  G06F1/3234 ,  G06F1/3206 ,  G09G5/14 ,  G06F3/0488 ,  H04W52/02 ,  G06F3/048

摘要： Provided is a method of providing information through a mobile device, in which an information providing screen is outputted only during the first activation performed within a predetermined time range designated by a user. Therefore, inconvenience resulting from repetitive outputs of the information providing screen can be resolved.

公开(公告)号：US09806028B2

公开(公告)日：2017-10-31

申请号：US14791812

申请日：2015-07-06

申请人： Jaekyu Lee ,  Kiseok Suh

发明人： Jaekyu Lee ,  Kiseok Suh

IPC分类号： H01L23/535 ,  H01L45/00 ,  H01L27/22 ,  H01L27/24 ,  H01L27/108

CPC分类号： H01L23/535 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device includes a device isolation in a trench that defines first to third active patterns that are spaced apart from each other and having a long axis parallel to a first direction, first and second word lines extending in a second direction perpendicular to the first direction, a bit line, and a source line. The first and second active patterns are arranged in the second direction to constitute a column. The third active pattern is at a side of the column. The first word line intersects the first and second active patterns. The second word line intersects the third active pattern. When viewed from a plan view, the bit line extends in the first direction between the first and third active patterns, and the source line extends in the first direction between the second and third active patterns.

公开(公告)号：US09082468B2

公开(公告)日：2015-07-14

申请号：US13692157

申请日：2012-12-03

申请人： Jaekyu Lee ,  Youngmin Kang ,  Hyunju Lee

发明人： Jaekyu Lee ,  Youngmin Kang ,  Hyunju Lee

IPC分类号： G11C8/00 ,  G11C8/10 ,  G11C11/16 ,  G11C8/08

CPC分类号： G11C8/10 ,  G11C8/08 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1659

摘要： High density semiconductor memory devices are provided. The device may include a cell array region including a lower structure, an upper structure, and a selection structure, the selection structure being interposed between the lower and upper structures and including word lines, and a decoding circuit controlling voltages applied to the word lines. The decoding circuit may be configured to apply a first voltage to a pair of the word lines adjacent to each other and to apply a second voltage different from the first voltage to the remaining ones of the word lines, in response to word line address information input thereto.

摘要翻译： 提供了高密度半导体存储器件。 该装置可以包括包括下部结构，上部结构和选择结构的单元阵列区域，所述选择结构插入在下部结构和上部结构之间并且包括字线，以及解码电路，其控制施加到字线的电压。 解码电路可以被配置为响应于字线地址信息输入，向彼此相邻的一对字线施加第一电压并且向剩余的字线施加不同于第一电压的第二电压 到此。

公开(公告)号：US09865342B2

公开(公告)日：2018-01-09

申请号：US14956478

申请日：2015-12-02

申请人： Jaekyu Lee

发明人： Jaekyu Lee

IPC分类号： G11C13/00 ,  G11C11/16

CPC分类号： G11C13/004 ,  G11C11/1655 ,  G11C11/1673 ,  G11C13/0026 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2213/79

摘要： A sensing circuit of a semiconductor memory device is provided which includes a bit line having a first edge and a second edge, a sensing line, a current supply unit, and a sense amplifier. A plurality of memory cells is connected between the first edge and the second edge. The sensing line is connected to the second edge of the bit line, and the current supply unit supplies a sensing current via the first edge of the bit line. The sense amplifier senses data stored at a selected memory cell by comparing a sensing voltage of the sensing line with a reference voltage when the sensing current flows to the selected memory cell from the first edge of the bit line.

公开(公告)号：US20120294065A1

公开(公告)日：2012-11-22

申请号：US13469740

申请日：2012-05-11

申请人： Sanghyun Hong ,  Jaekyu Lee ,  Yong Kwan Kim

发明人： Sanghyun Hong ,  Jaekyu Lee ,  Yong Kwan Kim

IPC分类号： G11C11/00 ,  H01L45/00

CPC分类号： H01L45/1683 ,  H01L27/101 ,  H01L27/224 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1273 ,  H01L45/1608 ,  H01L45/1675

摘要： According to an example embodiment, a variable resistance memory device includes a lower electrode that includes a spacer-shaped first sub lower electrode and a second sub lower electrode covering a curved sidewall of the first sub lower electrode. The second sub lower electrode extends upward to protrude above the top of the first sub lower electrode. The lower electrode includes an upward-tapered shape.

摘要翻译： 根据示例性实施例，可变电阻存储器件包括下电极，其包括间隔物形的第一副下电极和覆盖第一副下电极的弯曲侧壁的第二副下电极。 第二副下电极向上延伸以突出在第一子下电极的顶部之上。 下电极包括向上锥形的形状。

公开(公告)号：US10353665B2

公开(公告)日：2019-07-16

申请号：US15554196

申请日：2016-02-28

申请人： Jaekyu Lee ,  Jaelark Jung ,  Jaeyong Jang

发明人： Jaekyu Lee ,  Jaelark Jung ,  Jaeyong Jang

IPC分类号： G09G3/20 ,  G06F3/048 ,  G06F3/147 ,  G06Q30/02 ,  H04W52/02 ,  G06F3/0488

摘要： Provided is a method of providing information through a mobile device, in which an information providing screen is outputted only during the first activation performed within a predetermined time range designated by a user. Therefore, inconvenience resulting from repetitive outputs of the information providing screen can be resolved.

公开(公告)号：US20160088897A1

公开(公告)日：2016-03-31

申请号：US14497775

申请日：2014-09-26

申请人： Jaekyu Lee

发明人： Jaekyu Lee

IPC分类号： A43B13/36 ,  A43B3/02 ,  A43B3/24

CPC分类号： A43B13/36 ,  A43B3/246

摘要： “A sole shoe wearable over a boot includes: a sole having a top surface, a bottom surface and a sole edge line forming a first loop; a flange extending upwardly from and along the sole edge line to form a second loop above the first loop, where a groove is formed in an outer surface of the flange and along the sole edge line; and a grid structure formed in cross of side to side horizontal plates and front to rear vertical plates, on a rear part of the sole top surface, where a cross support is formed on and around each cross of the horizontal and vertical plates, where the horizontal and vertical plates are substantially incremental in height from around a center of the sole top surface toward the rear part of the sole top surface.”

摘要翻译： “穿着靴子的唯一的鞋子包括：鞋底，其具有形成第一环的顶表面，底表面和鞋底边缘线; 从鞋底边缘线向上延伸并沿着鞋底边缘线向上延伸的凸缘，以在第一环上方形成第二环，其中在凸缘的外表面中沿着鞋底边缘线形成凹槽; 以及在鞋底顶表面的后部形成在横向和横向的横向板和前后垂直板上的格栅结构，其中横向支撑形成在水平和垂直板的每个十字架上和周围，其中 水平和垂直板从鞋底顶表面的中心到鞋底顶表面的后部的高度基本上增加。

公开(公告)号：US08742388B2

公开(公告)日：2014-06-03

申请号：US13241826

申请日：2011-09-23

申请人： Jaekyu Lee

发明人： Jaekyu Lee

IPC分类号： H01L45/00

CPC分类号： H01L27/2463 ,  H01L27/2445

摘要： Variable resistance memory devices may include a semiconductor layer including first, second, third doped regions, a variable resistance pattern on the semiconductor layer, a lower electrode between the semiconductor layer and the variable resistance pattern, and a first metal silicide pattern in contact with the semiconductor layer. The third doped region may be spaced apart from the first metal silicide pattern, the first doped region may be spaced apart from the third doped region, and a second doped region may be interposed between the first and third doped regions and be in contact with the first metal silicide pattern. The first doped region may have the same conductivity type as the third doped region and a different conductivity type from the second doped region.

摘要翻译： 可变电阻存储器件可以包括半导体层，包括第一，第二，第三掺杂区域，半导体层上的可变电阻图案，半导体层和可变电阻图案之间的下电极，以及与第一金属硅化物图案接触的第一金属硅化物图案 半导体层。 第三掺杂区域可以与第一金属硅化物图案间隔开，第一掺杂区域可以与第三掺杂区域间隔开，并且第二掺杂区域可以插入在第一和第三掺杂区域之间并且与第二掺杂区域接触 第一金属硅化物图案。 第一掺杂区域可以具有与第三掺杂区域相同的导电类型和与第二掺杂区域不同的导电类型。

公开(公告)号：USD570088S1

公开(公告)日：2008-06-03

申请号：US29281646

申请日：2007-06-27

申请人： Jaekyu Lee

设计人： Jaekyu Lee