公开(公告)号：US20070232043A1

公开(公告)日：2007-10-04

申请号：US11395212

申请日：2006-04-03

申请人： Jyh-Huei Chen ,  Mei-Yun Wang ,  Tze-Liang Lee

发明人： Jyh-Huei Chen ,  Mei-Yun Wang ,  Tze-Liang Lee

IPC分类号： H01L21/4763

CPC分类号： H01L21/28518 ,  H01L21/28097 ,  H01L21/28202 ,  H01L29/4975 ,  H01L29/518 ,  H01L29/665 ,  H01L29/78

摘要： A method for forming a silicide layer on a substrate. A substrate with a silicon surface is provided. Nitrogen is incorporated into the silicon surface by a plasma treatment, to form a nitridized silicon surface. A metal layer is formed on the nitridized silicon surface. The substrate having the metal layer thereon is annealed to form a silicide layer between the metal layer and the substrate.

摘要翻译： 一种在衬底上形成硅化物层的方法。 提供具有硅表面的衬底。 通过等离子体处理将氮掺入硅表面，形成氮化硅表面。 在氮化硅表面上形成金属层。 对其上具有金属层的基板进行退火，以在金属层和基板之间形成硅化物层。

公开(公告)号：US10945916B2

公开(公告)日：2021-03-16

申请号：US16174265

申请日：2018-10-29

申请人： Mei-Yun Wang

发明人： Mei-Yun Wang

IPC分类号： A61H35/00 ,  A61N1/44 ,  A61H33/00

摘要： A foot spa includes a body and an electrolysis device. The body has a receiving space for containing water. The electrolysis device is mounted on a bottom of the body and includes a case, a control module and two electrolyte plates. The control module is mounted inside the body. The two electrolyte plates are mounted on a top portion of the case and are electrically connected to the control module. When the foot spa is operated, salt water is added to the receiving space for the two electrolyte plates to be soaked into the salt water in generation of an electrolytic reaction, such that sodium hydroxide and hypochlorous acid can be generated from the salt water to sterilize and deodorize the feet of users and provide the hygienic advantage.

公开(公告)号：US07795644B2

公开(公告)日：2010-09-14

申请号：US11649282

申请日：2007-01-04

申请人： Mei-Yun Wang ,  Cheng-Chen Hsueh ,  Wu-An Weng

发明人： Mei-Yun Wang ,  Cheng-Chen Hsueh ,  Wu-An Weng

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823412 ,  H01L21/823468 ,  H01L21/823864 ,  H01L27/105 ,  H01L27/1052 ,  H01L29/7843

摘要： Semiconductor devices with selective stress memory effect and fabrication methods thereof. The semiconductor device comprises a semiconductor substrate with a first region and a second region. Both the first region and the second region have a first doped region and a second doped region separated by an insulation layer. A PMOS transistor is disposed on the first doped region layer. An NMOS transistor is disposed on the second doped region. A first capping layer is disposed covering the NMOS transistor over the first region. A second capping layer is disposed covering the PMOS transistor over the first region. The thickness of the first capping layer is different from the thickness of the second capping layer, thereby different stress is induced on the PMOS transistor and the NMOS transistor respectively. The PMOS transistor and the NMOS transistor over the second region are silicided.

摘要翻译： 具有选择性应力记忆效应的半导体器件及其制造方法。 半导体器件包括具有第一区域和第二区域的半导体衬底。 第一区域和第二区域都具有由绝缘层隔开的第一掺杂区域和第二掺杂区域。 PMOS晶体管设置在第一掺杂区域层上。 NMOS晶体管设置在第二掺杂区域上。 第一覆盖层被设置为在第一区域上覆盖NMOS晶体管。 在第一区域上设置覆盖PMOS晶体管的第二覆盖层。 第一覆盖层的厚度与第二覆盖层的厚度不同，因此在PMOS晶体管和NMOS晶体管上分别产生不同的应力。 在第二区域上的PMOS晶体管和NMOS晶体管被硅化。

公开(公告)号：US07514348B2

公开(公告)日：2009-04-07

申请号：US11860639

申请日：2007-09-25

申请人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

发明人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

IPC分类号： H01L21/302

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76874 ,  H01L2221/1089

摘要： A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in the hole or trench by means of PVD. This is then followed by a sputter etching step which removes any overhang of this seed layer at the mouth of the trench or hole. A number of process variations are described including double etch/deposit steps, varying pressure and voltage in the same chamber to allow sputter etching and deposition to take place without breaking vacuum, and reduction of contact resistance between wiring levels by reducing via depth.

摘要翻译： 描述了在集成电路的表面处填充孔或沟槽而不在填充材料内捕获空隙的一般方法。 具体应用是用铜填充沟槽以形成镶嵌线。 首先，通过PVD将种子层沉积在孔或沟槽中。 然后进行溅射蚀刻步骤，其移除沟槽或孔口处的该种子层的任何突出端。 描述了许多工艺变化，包括双重蚀刻/沉积步骤，在相同的室中改变压力和电压，以允许在不破坏真空的情况下进行溅射蚀刻和沉积，并且通过减小通孔深度来降低布线水平之间的接触电阻。

公开(公告)号：US07205234B2

公开(公告)日：2007-04-17

申请号：US10772938

申请日：2004-02-05

申请人： Chii-Ming Wu ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

发明人： Chii-Ming Wu ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC分类号： H01L21/44

CPC分类号： H01L21/28052 ,  H01L21/28518 ,  H01L21/823835 ,  H01L29/665

摘要： A method of optimizing the formation of nickel silicide on regions of a MOSFET structure, has been developed. The method features formation of nickel silicide using an anneal procedure performed at a temperature below which nickel silicide instability and agglomeration occurs. A thin titanium interlayer is first formed on the MOSFET structure prior to nickel deposition, allowing an anneal procedure, performed after nickel deposition, to successfully form nickel silicide at a temperature of about 400° C. To obtain the desired conformality and thickness uniformity the thin titanium interlayer is formed via an atomic layer deposition procedure.

摘要翻译： 已经开发了在MOSFET结构的区域上优化硅化镍的形成的方法。 该方法的特征是使用在低于该温度的镍硅化物不稳定性和聚集发生的温度下进行的退火程序形成硅化镍。 首先在镍沉积之前在MOSFET结构上形成薄的钛中间层，允许在镍沉积之后进行的退火程序在约400℃的温度下成功形成硅化镍。为了获得所需的共形性和厚度均匀性，薄的 通过原子层沉积工艺形成钛夹层。

公开(公告)号：US20050277237A1

公开(公告)日：2005-12-15

申请号：US10867078

申请日：2004-06-14

申请人： Mei-Yun Wang ,  Chih-Wei Chang

发明人： Mei-Yun Wang ,  Chih-Wei Chang

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49

CPC分类号： H01L29/4933 ,  H01L21/28052

摘要： Deep silicidation of a polysilicon gate electrode following high temperature annealing of a source/drain under the gate may damage the gate oxide. This damage is prevented by forming the gate electrode as two polysilicon layers separated by a chemical oxide. During annealing the chemical oxide prevents the grains of one polysilicon layer from merging with the grains of the other polysilicon layer. Thereafter, silicidation is substantially confined to the top polysilicon layer, the low resistance of which shunts the bottom polysilicon layer through the chemical oxide.

摘要翻译： 在栅极下的源极/漏极的高温退火之后，多晶硅栅极的深硅化可能会损坏栅极氧化物。 通过将栅电极形成为由化学氧化物分离的两个多晶硅层来防止这种损伤。 在退火期间，化学氧化物防止一个多晶硅层的晶粒与另一个多晶硅层的晶粒结合。 此后，硅化物基本上限于顶部多晶硅层，其低电阻通过化学氧化物分流底部多晶硅层。

公开(公告)号：US20050272235A1

公开(公告)日：2005-12-08

申请号：US10859730

申请日：2004-06-03

申请人： Chii-Ming Wu ,  Cheng-Tung Lin ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

发明人： Chii-Ming Wu ,  Cheng-Tung Lin ,  Mei-Yun Wang ,  Chih-Wei Chang ,  Shau-Lin Shue

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/4763 ,  H01L29/49

CPC分类号： H01L21/28097 ,  H01L21/28518 ,  H01L29/4975 ,  H01L29/66507 ,  H01L29/785

摘要： A method of forming a silicided gate of a field effect transistor on a substrate having active regions is provided. The method includes the following steps: (a) forming a silicide in at least a first portion of a gate; (b) after step (a), depositing a metal over the active regions and said gate; and (c) annealing to cause the metal to react to form silicide in the active regions, wherein the thickness of said gate silicide is greater than the thickness of said silicide in said active regions.

摘要翻译： 提供了在具有有源区的基板上形成场效应晶体管的硅化物栅的方法。 该方法包括以下步骤：（a）在栅极的至少第一部分中形成硅化物; （b）在步骤（a）之后，在有源区域和所述栅极上沉积金属; 和（c）退火以引起金属反应以在有源区中形成硅化物，其中所述栅极硅化物的厚度大于所述有源区中所述硅化物的厚度。

公开(公告)号：US20050092598A1

公开(公告)日：2005-05-05

申请号：US10702970

申请日：2003-11-05

申请人： Mei-Yun Wang ,  Chih-Wei Chang ,  Chii-Ming Wu ,  Cheng-Tung Lin ,  Shau-Lin Shue

发明人： Mei-Yun Wang ,  Chih-Wei Chang ,  Chii-Ming Wu ,  Cheng-Tung Lin ,  Shau-Lin Shue

IPC分类号： C23C14/16 ,  H01L21/285 ,  C23C16/00 ,  C23C14/32

CPC分类号： H01L21/28518 ,  C23C14/16

摘要： A process for reducing the thermal budget and enhancing stability in the thermal budget of a metal salicide process used in the formation of metal salicides on substrates, thus eliminating or reducing salicide spiking and junction leakage in microelectronic devices fabricated on the substrates. According to a typical embodiment, a substrate is cooled to a sub-processing temperature which is lower than the metal deposition processing temperature and the salicide-forming metal is deposited onto the reduced-temperature substrate.

摘要翻译： 一种用于降低热预算并增强用于在基材上形成金属硅化物的金属硅化物工艺的热预算中的稳定性的方法，从而消除或减少在衬底上制造的微电子器件中的自杀剂尖峰和结漏电。 根据典型的实施方式，将基板冷却至比金属沉积处理温度低的副处理温度，并将形成自杀型化合物的金属沉积在还原温度基板上。

公开(公告)号：US06884669B2

公开(公告)日：2005-04-26

申请号：US10894542

申请日：2004-07-19

申请人： Chih-Wei Chang ,  Mei-Yun Wang

发明人： Chih-Wei Chang ,  Mei-Yun Wang

IPC分类号： H01L21/28 ,  H01L21/336

CPC分类号： H01L29/66507 ,  H01L21/28114 ,  H01L29/665 ,  H01L29/66545

摘要： Alternate methods of forming low resistance “hatted” polysilicon gate elements are provided that increase the effective area in the polysilicon gate for silicide grain growth during silicide formation. The expanded top portion helps to prevent silicide agglomeration in the silicide regions, thereby maintaining or reducing electrode resistance, improving high-frequency performance, and reducing gate delay in sub micron FET ULSI devices, without increasing the underlying active channel length.

摘要翻译： 提供了形成低电阻“帽”多晶硅栅极元件的替代方法，其增加了硅化物形成期间硅化物晶粒生长的多晶硅栅极中的有效面积。 扩展的顶部部分有助于防止硅化物区域中的硅化物聚集，从而在不增加潜在的有源沟道长度的情况下，保持或降低电极电阻，改善高频性能，并减小亚微米FET ULSI器件中的栅极延迟。

公开(公告)号：US06686280B1

公开(公告)日：2004-02-03

申请号：US09989802

申请日：2001-11-20

申请人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

发明人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

IPC分类号： H01L2100

CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76874 ,  H01L2221/1089

摘要： A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in the hole or trench by means of PVD. This is then followed by a sputter etching step which removes any overhang of this seed layer at the mouth of the trench or hole. A number of process variations are described including double etch/deposit steps, varying pressure and voltage in the same chamber to allow sputter etching and deposition to take place without breaking vacuum, and reduction of contact resistance between wiring levels by reducing via depth.