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    Bottle-neck recess in a semiconductor device
    4.
    发明授权
    Bottle-neck recess in a semiconductor device 有权
    半导体器件中的瓶颈凹槽

    公开(公告)号：US09054130B2

    公开(公告)日：2015-06-09

    申请号：US12841763

    申请日：2010-07-22

    申请人： Eric Peng ,  Chao-Cheng Chen ,  Ming-Hua Yu ,  Ying Hao Hsieh ,  Tze-Liang Lee ,  Chii-Horng Li ,  Syun-Ming Jang ,  Shih-Hao Lo

    发明人： Eric Peng ,  Chao-Cheng Chen ,  Ming-Hua Yu ,  Ying Hao Hsieh ,  Tze-Liang Lee ,  Chii-Horng Li ,  Syun-Ming Jang ,  Shih-Hao Lo

    IPC分类号： H01L21/302 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/165

    CPC分类号： H01L29/7848 ,  H01L21/30608 ,  H01L21/3065 ,  H01L29/165 ,  H01L29/66636

    摘要： The present disclosure provides a method for fabricating a semiconductor device that includes providing a silicon substrate, forming a gate stack over the silicon substrate, performing a biased dry etching process to the substrate to remove a portion of the silicon substrate, thereby forming a recess region in the silicon substrate, performing a non-biased etching process to the recess region in the silicon substrate, thereby forming a bottle-neck shaped recess region in the silicon substrate, and epi-growing a semiconductor material in the bottle-neck shaped recess region in the silicon substrate. An embodiment may include a biased dry etching process including adding HeO2 gas and HBr gas. An embodiment may include performing a first biased dry etching process including N2 gas and performing a second biased dry etching process not including N2 gas. An embodiment may include performing an oxidation process to the recess region in the silicon substrate by adding oxygen gas to form silicon oxide on a portion of the recess region in the silicon substrate. As such, these processes form polymer protection to help form the bottle-neck shaped recess.

    摘要翻译： 本公开提供了一种制造半导体器件的方法，其包括提供硅衬底，在硅衬底上形成栅极堆叠，对衬底执行偏置的干蚀刻工艺以去除硅衬底的一部分，从而形成凹陷区域 在硅衬底中，对硅衬底中的凹陷区域进行非偏置蚀刻工艺，从而在硅衬底中形成瓶颈形凹部区域，并且在瓶颈形凹部区域中生长半导体材料 在硅衬底中。 一个实施例可以包括偏置的干蚀刻工艺，包括加入HeO2气体和HBr气体。 实施例可以包括执行包括N 2气体的第一偏压干法蚀刻工艺，并执行不包括N 2气体的第二偏压干式蚀刻工艺。 一个实施例可以包括通过在硅衬底中的一部分凹陷区域上添加氧气以形成氧化硅，来对硅衬底中的凹陷区域进行氧化处理。 因此，这些方法形成聚合物保护以帮助形成瓶颈形凹部。

    Method of temperature determination for deposition reactors
    5.
    发明授权
    Method of temperature determination for deposition reactors 有权
    沉积反应器温度测定方法

    公开(公告)号：US09011599B2

    公开(公告)日：2015-04-21

    申请号：US12835789

    申请日：2010-07-14

    申请人： Jhi-Cherng Lu ,  Jr-Hung Li ,  Chii-Horng Li ,  Pang-Yen Tsai ,  Bing-Hung Chen ,  Tze-Liang Lee

    发明人： Jhi-Cherng Lu ,  Jr-Hung Li ,  Chii-Horng Li ,  Pang-Yen Tsai ,  Bing-Hung Chen ,  Tze-Liang Lee

    IPC分类号： C30B25/08 ,  C30B25/16 ,  C30B29/06 ,  C30B29/08 ,  C30B29/52 ,  H01L21/02 ,  H01L21/66

    CPC分类号： C30B25/16 ,  C30B29/06 ,  C30B29/08 ,  C30B29/52 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L22/10 ,  H01L22/12 ,  Y10T117/1004 ,  Y10T117/1008

    摘要： A method of determining a temperature in a deposition reactor includes the steps of depositing a first epitaxial layer of silicon germanium on a substrate, depositing a second epitaxial layer of silicon above the first epitaxial layer, measuring the thickness of the second epitaxial layer and determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer. The method may also include heating the deposition reactor to approximately a predetermined temperature using a heating device and a temperature measuring device and generating a signal indicative of a temperature within the deposition reactor. The method may also contain the steps of comparing the measured thickness with a predetermined thickness of the second epitaxial layer corresponding to the predetermined temperature and determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer and the predetermined thickness of the second epitaxial layer.

    摘要翻译： 确定沉积反应器中的温度的方法包括以下步骤：将硅锗的第一外延层沉积在衬底上，在第一外延层上沉积硅的第二外延层，测量第二外延层的厚度并确定 使用测量的第二外延层的厚度在沉积反应器中进行温度测量。 该方法还可以包括使用加热装置和温度测量装置将沉积反应器加热至约预定温度，并产生指示沉积反应器内的温度的信号。 该方法还可以包括以下步骤：将测量的厚度与对应于预定温度的第二外延层的预定厚度进行比较，并使用第二外延层的测量厚度和第二外延层的预定厚度来确定沉积反应器中的温度 外延层。

    CMOS dual metal gate semiconductor device
    7.
    发明授权
    CMOS dual metal gate semiconductor device 有权
    CMOS双金属栅极半导体器件

    公开(公告)号：US08836038B2

    公开(公告)日：2014-09-16

    申请号：US12883241

    申请日：2010-09-16

    申请人： Yong-Tian Hou ,  Peng-Fu Hsu ,  Jin Ying ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Tze-Liang Lee

    发明人： Yong-Tian Hou ,  Peng-Fu Hsu ,  Jin Ying ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Tze-Liang Lee

    IPC分类号： H01L29/78 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66

    CPC分类号： H01L21/823842 ,  H01L21/28044 ,  H01L21/28088 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7843

    摘要： A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.

    摘要翻译： 提供半导体结构及其形成方法。 半导体结构包括第一导电类型的第一MOS器件和与第一导电类型相反的第二导电类型的第二MOS器件。 第一MOS器件包括在半导体衬底上的第一栅极电介质; 在所述第一栅极电介质上的第一含金属的栅电极层; 以及位于第一含金属栅电极层上的硅化物层。 第二MOS器件包括半导体衬底上的第二栅极电介质; 在所述第二栅极电介质上方的第二含金属的栅电极层; 以及具有位于所述第二含金属栅电极层上的部分的接触蚀刻停止层，其中所述接触蚀刻停止层的所述部分和所述第二含金属栅电极层之间的区域基本上不含硅。

    MOSFET device with localized stressor
    8.
    发明授权
    MOSFET device with localized stressor 有权
    具有局部应力源的MOSFET器件

    公开(公告)号：US08557669B2

    公开(公告)日：2013-10-15

    申请号：US12176655

    申请日：2008-07-21

    申请人： Chien-Hao Chen ,  Pang-Yen Tsai ,  Chie-Chien Chang ,  Tze-Liang Lee ,  Shih-Chang Chen

    发明人： Chien-Hao Chen ,  Pang-Yen Tsai ,  Chie-Chien Chang ,  Tze-Liang Lee ,  Shih-Chang Chen

    IPC分类号： H01L21/42

    CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/45 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

    摘要： MOSFETs having localized stressors are provided. The MOSFET has a stress-inducing layer formed in the source/drain regions, wherein the stress-inducing layer comprises a first semiconductor material and a second semiconductor material. A treatment is performed on the stress-inducing layer such that a reaction is caused with the first semiconductor material and the second semiconductor material is forced lower into the stress-inducing layer. The stress-inducing layer may be either a recessed region or non-recessed region. A first method involves forming a stress-inducing layer, such as SiGe, in the source/drain regions and performing a nitridation or oxidation process. A nitride or oxide film is formed in the top portion of the stress-inducing layer, forcing the Ge lower into the stress-inducing layer. Another method embodiment involves forming a reaction layer over the stress-inducing layer and performing a treatment process to cause the reaction layer to react with the stress-inducing layer.

    摘要翻译： 提供具有局部应力的MOSFET。 MOSFET具有形成在源极/漏极区域中的应力诱导层，其中应力诱导层包括第一半导体材料和第二半导体材料。 对应力诱导层进行处理，使得由第一半导体材料引起反应，并且第二半导体材料被迫下降到应力诱导层中。 应力诱导层可以是凹陷区域或非凹陷区域。 第一种方法包括在源极/漏极区域中形成诸如SiGe的应力诱导层并进行氮化或氧化过程。 在应力诱导层的顶部形成氮化物或氧化物膜，迫使Ge较低进入应力诱导层。 另一方法实施例涉及在应力诱导层上形成反应层，并进行处理工艺以使反应层与应力诱导层反应。

    Method for fabricating a semiconductor device
    9.
    发明授权
    Method for fabricating a semiconductor device 有权
    半导体器件的制造方法

    公开(公告)号：US08530316B2

    公开(公告)日：2013-09-10

    申请号：US13736453

    申请日：2013-01-08

    申请人： Yu-Hung Cheng ,  Jhi-Cherng Lu ,  Ming-Hua Yu ,  Chii-Horng Li ,  Tze-Liang Lee

    发明人： Yu-Hung Cheng ,  Jhi-Cherng Lu ,  Ming-Hua Yu ,  Chii-Horng Li ,  Tze-Liang Lee

    IPC分类号： H01L21/336

    CPC分类号： H01L21/20 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66477 ,  H01L29/7848

    摘要： A method for fabricating a semiconductor device, the method including growing a first semiconductor structure comprising a first semiconductor material on a surface of a substrate, wherein growing the first semiconductor structure includes forming a semiconductor particle comprising the first semiconductor material on a second semiconductor structure of the semiconductor device. The method further includes forming a protection layer of a second semiconductor material on the first semiconductor structure, wherein forming the protection layer includes forming the protection layer on the semiconductor particle. The method further includes removing a portion of the protection layer, wherein removing the portion of the protection layer includes fully removing the protection layer on the semiconductor particle and the semiconductor particle.

    摘要翻译： 一种制造半导体器件的方法，所述方法包括在衬底的表面上生长包括第一半导体材料的第一半导体结构，其中生长第一半导体结构包括在第二半导体结构的第二半导体结构上形成包含第一半导体材料的半导体粒子 半导体器件。 该方法还包括在第一半导体结构上形成第二半导体材料的保护层，其中形成保护层包括在半导体颗粒上形成保护层。 该方法还包括去除保护层的一部分，其中去除保护层的部分包括完全去除半导体颗粒和半导体颗粒上的保护层。

    Reducing Variation by Using Combination Epitaxy Growth
    10.
    发明申请
    Reducing Variation by Using Combination Epitaxy Growth 有权
    通过组合外延生长减少变异

    公开(公告)号：US20110287611A1

    公开(公告)日：2011-11-24

    申请号：US13030850

    申请日：2011-02-18

    申请人： Yu-Hung Cheng ,  Chii-Horng Li ,  Tze-Liang Lee ,  Yi-Hung Lin

    发明人： Yu-Hung Cheng ,  Chii-Horng Li ,  Tze-Liang Lee ,  Yi-Hung Lin

    IPC分类号： H01L21/20

    CPC分类号： H01L29/66636 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L29/0847 ,  H01L29/7848

    摘要： A method for forming a semiconductor structure includes forming a gate stack over a semiconductor substrate in a wafer; forming a recess in the semiconductor substrate and adjacent the gate stack; and performing a selective epitaxial growth to grow a semiconductor material in the recess to form an epitaxy region. The step of performing the selective epitaxial growth includes performing a first growth stage with a first growth-to-etching (E/G) ratio of process gases used in the first growth stage; and performing a second growth stage with a second E/G ratio of process gases used in the second growth stage different from the first E/G ratio.

    摘要翻译： 一种用于形成半导体结构的方法包括在晶片上的半导体衬底上形成栅叠层; 在所述半导体衬底中形成凹槽并邻近所述栅叠层; 以及进行选择性外延生长以在所述凹部中生长半导体材料以形成外延区域。 执行选择性外延生长的步骤包括以第一生长阶段中使用的工艺气体的第一生长蚀刻（E / G）比率进行第一生长阶段; 以及在与第一E / G比不同的第二生长阶段中使用的处理气体的第二E / G比进行第二生长阶段。