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公开(公告)号：US20160268298A1
公开(公告)日：2016-09-15
申请号：US14849743
申请日：2015-09-10
发明人： Tadashi IGUCHI , Murato Kawai , Toru Matsuda , Hisashi Kato , Megumi Ishiduki
IPC分类号： H01L27/115 , H01L23/522 , H01L21/311 , G11C16/04 , H01L21/02
CPC分类号： H01L27/11582 , G11C16/0483 , H01L23/5226 , H01L27/11565 , H01L27/11575
摘要： A semiconductor memory device according to an embodiment includes a memory cell array configured to have a memory string obtained by connecting first selection transistors, memory transistors, and second selection transistors in series. When three directions crossing each other are set to first, second, and third directions, respectively, the memory cell array has first conductive layers to be control gates of the first selection transistors, second conductive layers to be control gates of the memory transistors, and third conductive layers to be control gates of the second selection transistors, which are laminated in the third direction. Ends of the first conductive layers and ends of the third conductive layers are formed in shapes of steps extending in the first direction and ends of the second conductive layers are formed in shapes of steps extending in both directions of the first direction and the second direction.
摘要翻译： 根据实施例的半导体存储器件包括存储单元阵列，其被配置为具有通过串联连接第一选择晶体管，存储晶体管和第二选择晶体管而获得的存储器串。 当彼此交叉的三个方向分别设置为第一，第二和第三方向时，存储单元阵列具有作为第一选择晶体管的控制栅极的第一导电层，作为存储晶体管的控制栅极的第二导电层，以及 第三导电层作为第二选择晶体管的控制栅极，其在第三方向上层叠。 第一导电层的端部和第三导电层的端部形成为在第一方向上延伸的台阶形状，并且第二导电层的端部形成为在第一方向和第二方向的两个方向上延伸的台阶形状。
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2.发明授权公开(公告)号：US09312134B2
公开(公告)日：2016-04-12
申请号：US14150504
申请日：2014-01-08
发明人： Yoshiaki Fukuzumi , Ryota Katsumata , Masaru Kito , Masaru Kidoh , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Tomoko Fujiwara , Hideaki Aochi , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
IPC分类号： H01L29/792 , H01L21/223 , H01L27/115 , H01L29/66 , H01L21/265 , H01L29/78
CPC分类号： H01L27/11582 , H01L21/223 , H01L21/265 , H01L27/11578 , H01L29/04 , H01L29/1037 , H01L29/16 , H01L29/42344 , H01L29/4916 , H01L29/66666 , H01L29/66833 , H01L29/7827 , H01L29/792 , H01L29/7926
摘要： A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.
摘要翻译： 一种非易失性半导体存储器件，包括：堆叠结构单元，包括在第一方向上交替地堆叠有多个电极膜的多个绝缘膜; 选择栅极电极，其沿所述第一方向堆叠在所述层叠结构单元上; 绝缘层，其沿所述第一方向堆叠在所述选择栅电极上; 第一半导体柱在第一方向上穿透层叠结构单元，选择栅电极和绝缘层，第一半导体柱的第一截面具有环形构造，第一横截面在垂直于 第一方向 第一核心单元，其被埋在第一半导体柱的内侧，第一芯单元从绝缘层的上表面凹入; 以及设置在所述第一芯单元上以接触所述第一芯单元的所述第一半导体柱的第一导电层。
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3.发明申请公开(公告)号：US20140284685A1
公开(公告)日：2014-09-25
申请号：US13969809
申请日：2013-08-19
发明人： Yoshiro SHIMOJO , Tsuneo Uenaka , Megumi Ishiduki , Mitsuru Sato
IPC分类号： H01L29/792 , H01L21/28 , H01L29/66
CPC分类号： H01L29/66833 , H01L27/1157 , H01L27/11582 , H01L29/7926
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes: a stacked body including each of a plurality of electrode layers and each of a plurality of insulating layers stacked alternately; a first interlayer insulating film; a select gate electrode; a second interlayer insulating film; a pair of semiconductor layers; a first insulating film; a second insulating film; a third interlayer insulating film; a first contact electrode connected to one upper end of the pair of semiconductor layers; a second contact electrode connected to the other upper end of the pair of semiconductor layers; a third contact electrode connected to the second contact electrode; a first interconnect layer connected to the first contact electrode; and a second interconnect layer connected to the third contact electrode.
摘要翻译： 根据一个实施例，非易失性半导体存储器件包括：堆叠体，其包括交替堆叠的多个电极层和多个绝缘层中的每一个; 第一层间绝缘膜; 选择栅电极; 第二层间绝缘膜; 一对半导体层; 第一绝缘膜; 第二绝缘膜; 第三层间绝缘膜; 与所述一对半导体层的一个上端连接的第一接触电极; 连接到所述一对半导体层的另一个上端的第二接触电极; 连接到所述第二接触电极的第三接触电极; 连接到所述第一接触电极的第一互连层; 以及连接到第三接触电极的第二互连层。
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4.发明申请公开(公告)号：US20140117434A1
公开(公告)日：2014-05-01
申请号：US14150504
申请日：2014-01-08
发明人： Yoshiaki Fukuzumi , Ryota Katsumata , Masaru Kito , Masaru Kidoh , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Tomoko Fujiwara , Hideaki Aochi , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
IPC分类号： H01L27/115 , H01L21/265 , H01L29/66 , H01L21/223 , H01L29/78 , H01L29/792
CPC分类号： H01L27/11582 , H01L21/223 , H01L21/265 , H01L27/11578 , H01L29/04 , H01L29/1037 , H01L29/16 , H01L29/42344 , H01L29/4916 , H01L29/66666 , H01L29/66833 , H01L29/7827 , H01L29/792 , H01L29/7926
摘要： A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.
摘要翻译： 一种非易失性半导体存储器件，包括：堆叠结构单元，包括在第一方向上交替地堆叠有多个电极膜的多个绝缘膜; 选择栅极电极，其沿所述第一方向堆叠在所述层叠结构单元上; 绝缘层，其沿所述第一方向堆叠在所述选择栅电极上; 第一半导体柱在第一方向上穿透层叠结构单元，选择栅电极和绝缘层，第一半导体柱的第一截面具有环形构造，第一横截面在垂直于 第一方向 第一核心单元，其被埋在第一半导体柱的内侧，第一芯单元从绝缘层的上表面凹入; 以及设置在所述第一芯单元上以接触所述第一芯单元的所述第一半导体柱的第一导电层。
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公开(公告)号：US20140038396A1
公开(公告)日：2014-02-06
申请号：US14048495
申请日：2013-10-08
发明人： Megumi Ishiduki , Ryota Katsumata , Tomo Ohsawa , Mitsuru Sato , Masaru Kidoh , Hiroyasu Tanaka
IPC分类号： H01L21/425
CPC分类号： H01L21/425 , H01L27/11582 , H01L29/7926
摘要： According to one embodiment, a semiconductor device includes a substrate, a first stacked body, a memory film, a first channel body, a second stacked body, a gate insulating film and a second channel body. A step part is formed between a side face of the select gate and the second insulating layer. A film thickness of a portion covering the step part of the second channel body is thicker than a film thickness of a portion provided between the second insulating layers of the second channel body.
摘要翻译： 根据一个实施例，半导体器件包括衬底，第一层叠体，存储膜，第一通道体，第二堆叠体，栅极绝缘膜和第二通道体。 在选择栅极的侧面和第二绝缘层之间形成台阶部。 覆盖第二通道体的台阶部分的部分的膜厚比设置在第二通道体的第二绝缘层之间的部分的膜厚度厚。
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公开(公告)号：US20130126961A1
公开(公告)日：2013-05-23
申请号：US13740803
申请日：2013-01-14
发明人： Yoshiaki FUKUZUMI , Ryota Katsumata , Masaru Kidoh , Masaru Kito , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Hideaki Aochi
IPC分类号： H01L27/105
CPC分类号： H01L27/11582 , G11C16/0483 , H01L27/1052 , H01L27/11551 , H01L27/11556 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L29/513
摘要： A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.
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公开(公告)号：USRE45840E1
公开(公告)日：2016-01-12
申请号：US14327359
申请日：2014-07-09
发明人： Ryota Katsumata , Hideaki Aochi , Hiroyasu Tanaka , Masaru Kito , Yoshiaki Fukuzumi , Masaru Kidoh , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Tomoko Fujiwara , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
IPC分类号： G11C11/14 , H01L27/115 , G11C16/04 , G11C16/06
CPC分类号： H01L27/11578 , G11C16/0466 , G11C16/06 , H01L27/11565 , H01L27/11582
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit. The stacked body is provided on the substrate. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. A through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in an interior of the through-hole. The charge storage film is provided between the electrode film and the semiconductor pillar. The drive circuit supplies a potential to the electrode film. The diameter of the through-hole differs by a position in the stacking direction. The drive circuit supplies a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.
摘要翻译： 根据一个实施例，非易失性半导体存储器件包括衬底，堆叠体，半导体柱，电荷存储膜和驱动电路。 层叠体设置在基板上。 层叠体包括交替层叠有多个电极膜的多个绝缘膜。 在堆叠体中形成通孔，以在堆叠方向上对齐。 半导体柱被埋在通孔的内部。 电荷存储膜设置在电极膜和半导体柱之间。 驱动电路向电极膜提供电位。 通孔的直径与层叠方向的位置不同。 当穿透电极膜的通孔的直径减小时，驱动电路提供降低与半导体柱的电位差的电位。
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公开(公告)号：US09054132B2
公开(公告)日：2015-06-09
申请号：US13930401
申请日：2013-06-28
发明人： Mitsuru Sato , Masaru Kito , Megumi Ishiduki , Ryota Katsumata
IPC分类号： H01L21/336 , H01L29/66 , H01L29/78 , H01L27/115 , H01L29/792 , H01L29/06
CPC分类号： H01L27/11582 , H01L27/1157 , H01L29/0657 , H01L29/42344 , H01L29/66666 , H01L29/66833 , H01L29/7827 , H01L29/792 , H01L29/7926
摘要： According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The second insulating film seals the hole near an interface of the insulating layer and the select gate. The second insulating film is provided on a side wall of the channel body with a space left in the hole above the select gate. The method can include burying a semiconductor film in the space, in addition, forming a conductive film in contact with the channel body.
摘要翻译： 根据一个实施例，公开了一种用于制造半导体器件的方法。 第二绝缘膜密封绝缘层和选择栅极的界面附近的孔。 第二绝缘膜设置在通道主体的侧壁上，在选通门上方的孔中留有空间。 该方法可以包括在该空间内埋入半导体膜，此外，形成与通道体接触的导电膜。
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9.发明授权公开(公告)号：US08729624B2
公开(公告)日：2014-05-20
申请号：US13740803
申请日：2013-01-14
发明人： Yoshiaki Fukuzumi , Ryota Katsumata , Masaru Kidoh , Masaru Kito , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Hideaki Aochi
IPC分类号： H01L21/336 , H01L29/792
CPC分类号： H01L27/11582 , G11C16/0483 , H01L27/1052 , H01L27/11551 , H01L27/11556 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L29/513
摘要： A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.
摘要翻译： 非挥发性半导体存储装置具有多个存储串，其中多个电可重写存储单元串联连接。 每个存储串包括第一半导体层，每个第一半导体层具有相对于衬底在垂直方向上延伸的一对柱状部分和形成为耦合该对柱状部分的下端的耦合部分; 形成为围绕所述柱状部的侧面的电荷存储层; 以及形成为围绕柱状部分和电荷存储层的侧表面的第一导电层。 第一导电层用作存储器单元的栅电极。
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10.发明申请公开(公告)号：US20130228850A1
公开(公告)日：2013-09-05
申请号：US13857690
申请日：2013-04-05
发明人： Hiroyasu TANAKA , Hideaki Aochi , Ryota Katsumata , Masaru Kidoh , Masaru Kito , Yoshiaki Fukuzumi , Yosuke Komori , Megumi Ishiduki , Tomoko Fujiwara , Junya Matsunami , Ryouhei Kirisawa
IPC分类号： H01L29/792 , H01L29/66
CPC分类号： H01L29/792 , H01L27/11578 , H01L27/11582 , H01L29/66833
摘要： A nonvolatile semiconductor memory device includes: a semiconductor substrate; a stacked body provided on the semiconductor substrate, the stacked body having electrode films and insulating films being alternately stacked; a first and second semiconductor pillars; and a first and second charge storage layers. The first and second semiconductor pillars are provided inside a through hole penetrating through the stacked body in a stacking direction of the stacked body. The through hole has a cross section of an oblate circle, when cutting in a direction perpendicular to the stacking direction. The first and second semiconductor pillars face each other in a major axis direction of the first oblate circle. The first and second semiconductor pillars extend in the stacking direction. The first and second charge storage layers are provided between the electrode film and the first and second semiconductor pillars, respectively.
摘要翻译： 非易失性半导体存储器件包括：半导体衬底; 设置在所述半导体基板上的层叠体，具有交替堆叠的电极膜和绝缘膜的层叠体， 第一和第二半导体柱; 以及第一和第二电荷存储层。 第一半导体柱和第二半导体柱设置在层叠体的层叠方向上贯穿层叠体的贯通孔内。 当沿垂直于堆叠方向的方向切割时，通孔具有扁圆形的横截面。 第一和第二半导体柱在第一扁圆的长轴方向上彼此面对。 第一和第二半导体柱沿层叠方向延伸。 第一和第二电荷存储层分别设置在电极膜和第一和第二半导体柱之间。
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