-
公开(公告)号：US09741738B2
公开(公告)日：2017-08-22
申请号：US15141135
申请日：2016-04-28
发明人： Yoshiaki Fukuzumi , Ryota Katsumata , Masaru Kidoh , Masaru Kito , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Hideaki Aochi
IPC分类号： H01L29/51 , H01L27/11 , H01L27/11582 , G11C16/04 , H01L27/11556 , H01L27/11573 , H01L27/11578 , H01L27/105 , H01L27/11575 , H01L27/11551
CPC分类号： H01L27/11582 , G11C16/0483 , H01L27/1052 , H01L27/11551 , H01L27/11556 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L29/513
摘要： A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.
-
公开(公告)号：US09666595B2
公开(公告)日：2017-05-30
申请号：US14865873
申请日：2015-09-25
发明人： Ryosuke Sawabe , Hanae Ishihara , Masaru Kito
IPC分类号： H01L27/10 , H01L27/11582 , H01L27/11578 , H01L27/11551 , H01L27/11514 , H01L27/11575 , H01L27/11556 , H01L21/28 , H01L27/11548
CPC分类号： H01L27/11582 , H01L21/28273 , H01L21/28282 , H01L27/11514 , H01L27/11548 , H01L27/11551 , H01L27/11556 , H01L27/11575 , H01L27/11578 , H01L2924/1438
摘要： A semiconductor memory device includes a first layer, a plurality of memory areas, a plurality of contact wires, a first shunt wire, and a second shunt wire. The memory areas are provided on the first layer in a first direction. The contact wires have a longitudinal direction in a second direction perpendicular to the first layer. The contact wires are provided between the adjacent memory areas on the first layer in a third direction intersecting the first direction. The first shunt wire commonly connects the contact wires. The second shunt wire extends in the first direction and is electrically connected to the first shunt wire.
-
公开(公告)号：US20170053924A1
公开(公告)日：2017-02-23
申请号：US15334828
申请日：2016-10-26
发明人： Naoki YASUDA , Masaru Kito
IPC分类号： H01L27/115 , H01L21/28
CPC分类号： H01L27/1157 , H01L21/28282 , H01L27/11568 , H01L27/11573 , H01L27/11582 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/792 , H01L29/7926
摘要： According to one embodiment, a control gate is formed on the semiconductor substrate and includes a cylindrical through hole. A block insulating film, a charge storage film, a tunnel insulating film, and a semiconductor layer are formed on a side surface of the control gate inside the through hole. The tunnel insulating film comprises a first insulating film having SiO2 as a base material and containing an element that lowers a band gap of the base material by being added. A density and a density gradient of the element monotonously increase from the semiconductor layer toward the charge storage film.
摘要翻译： 根据一个实施例，控制栅极形成在半导体衬底上并且包括圆柱形通孔。 在通孔内的控制栅极的侧表面上形成块绝缘膜，电荷存储膜，隧道绝缘膜和半导体层。 隧道绝缘膜包括具有SiO 2作为基材的第一绝缘膜，并且包含通过添加来降低基材的带隙的元素。 元素的密度和密度梯度从半导体层向电荷存储膜单调增加。
-
公开(公告)号：US08873296B2
公开(公告)日：2014-10-28
申请号：US13953376
申请日：2013-07-29
发明人： Kiyotaro Itagaki , Masaru Kito , Ryu Ogiwara , Hitoshi Iwai
IPC分类号： G11C16/04 , H01L27/115 , G11C16/10 , G11C16/16
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/30 , G11C16/344 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11582
摘要： A control circuit is configured to execute an erasing operation on a selected cell unit in a selected memory block. In the erasing operation, the control circuit raises the voltage of the bodies of the first memory transistors included in the selected cell unit to a first voltage, sets the voltage of the bodies of the first memory transistors included in the non-selected cell unit to a second voltage lower than the first voltage, and applies a third voltage equal to or lower than the second voltage to the gates of the first memory transistors included in the selected cell unit and the non-selected cell unit.
摘要翻译： 控制电路被配置为对选择的存储块中的所选择的单元单元执行擦除操作。 在擦除操作中，控制电路将包括在所选择的单元单元中的第一存储晶体管的主体的电压升高到第一电压，将未选择的单元单元中包括的第一存储晶体管的主体的电压设置为 第二电压低于第一电压，并将等于或低于第二电压的第三电压施加到所选择的单元单元和未选择的单元单元中包括的第一存储晶体管的栅极。
-
公开(公告)号：US08654586B2
公开(公告)日：2014-02-18
申请号：US13737480
申请日：2013-01-09
发明人： Masaru Kito , Ryota Katsumata , Yoshiaki Fukuzumi , Masaru Kidoh , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Tomoko Fujiwara , Hideaki Aochi , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
IPC分类号： G11C16/04
CPC分类号： G11C16/04 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/3409 , G11C16/3413 , H01L27/11578 , H01L27/11582
摘要： A nonvolatile semiconductor memory device includes a memory unit and a control unit. The memory unit includes a multilayer structure including electrode films and inter-electrode insulating films alternately stacked in a first direction; a semiconductor pillar piercing the multilayer structure in the first direction; a memory layer provided between the semiconductor pillar and the electrode films; an inner insulating film provided between the memory layer and the semiconductor pillar; an outer insulating film provided between the memory layer and the electrode films; and a wiring electrically connected to the first semiconductor pillar. In an erasing operation, the control unit sets the first wiring at a first potential and sets the electrode film at a second potential lower than the first potential, and then sets the first wiring at a third potential and sets the electrode film at a fourth potential higher than the third potential.
摘要翻译： 非易失性半导体存储器件包括存储器单元和控制单元。 存储单元包括多层结构，其包括沿第一方向交替堆叠的电极膜和电极间绝缘膜; 在所述第一方向上穿透所述多层结构的半导体柱; 设置在所述半导体柱和所述电极膜之间的存储层; 设置在所述存储层和所述半导体柱之间的内部绝缘膜; 设置在所述存储层和所述电极膜之间的外部绝缘膜; 以及电连接到第一半导体柱的布线。 在擦除操作中，控制单元将第一布线设置在第一电位，并将电极膜设置在低于第一电位的第二电位，然后将第一布线设置在第三电位，并将电极膜设置为第四电位 高于第三个潜力。
-
公开(公告)号：US20140001544A1
公开(公告)日：2014-01-02
申请号：US13930401
申请日：2013-06-28
发明人： Mitsuru Sato , Masaru Kito , Megumi Ishiduki , Ryota Katsumata
CPC分类号： H01L27/11582 , H01L27/1157 , H01L29/0657 , H01L29/42344 , H01L29/66666 , H01L29/66833 , H01L29/7827 , H01L29/792 , H01L29/7926
摘要： According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The second insulating film seals the hole near an interface of the insulating layer and the select gate. The second insulating film is provided on a side wall of the channel body with a space left in the hole above the select gate. The method can include burying a semiconductor film in the space, in addition, forming a conductive film in contact with the channel body.
摘要翻译： 根据一个实施例，公开了一种用于制造半导体器件的方法。 第二绝缘膜密封绝缘层和选择栅极的界面附近的孔。 第二绝缘膜设置在通道主体的侧壁上，在选通门上方的孔中留有空间。 该方法可以包括在该空间内埋入半导体膜，此外，形成与通道体接触的导电膜。
-
公开(公告)号：US10211219B2
公开(公告)日：2019-02-19
申请号：US15666653
申请日：2017-08-02
发明人： Masaru Kito , Hideaki Aochi , Ryota Katsumata , Akihiro Nitayama , Masaru Kidoh , Hiroyasu Tanaka , Yoshiaki Fukuzumi , Yasuyuki Matsuoka , Mitsuru Sato
IPC分类号： H01L27/32 , H01L27/11582 , H01L21/822 , H01L27/06 , H01L27/105 , H01L27/115 , H01L27/11573 , H01L27/11578 , H01L27/11556 , G11C16/04
摘要： A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.
-
公开(公告)号：US20170243884A1
公开(公告)日：2017-08-24
申请号：US15263739
申请日：2016-09-13
发明人： Hiroshi Nakaki , Masaru Kito
IPC分类号： H01L27/115 , H01L23/373
CPC分类号： H01L27/11582 , H01L23/373 , H01L28/00
摘要： According to the embodiment, a semiconductor device includes: a stacked body; a columnar portion, an insulating portion; and wall portion. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The columnar portion is provided in the stacked body and extends in a staking direction of the stacked body. The insulating portion is provided around the stacked body and surrounds the stacked body. The wall portion is provided in the insulating portion and is separated from the stacked body. The wall portion extends in the stacking direction and in a first direction crossing the stacking direction.
-
公开(公告)号：US20160284727A1
公开(公告)日：2016-09-29
申请号：US14834636
申请日：2015-08-25
发明人： Takeshi SONEHARA , Masaru Kito
IPC分类号： H01L27/115 , H01L23/535 , H01L23/528
CPC分类号： H01L27/11582 , H01L23/528 , H01L23/535 , H01L27/1157 , H01L27/11575
摘要： According to an embodiment, a semiconductor memory device comprises a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are stacked on a substrate. The semiconductor layer has one end connected to the substrate, has as its longer direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. Assuming at least one control gate electrode positioned in a lowermost layer of the plurality of control gate electrodes to be a first control gate electrode, the first control gate electrode comprises: a first portion; a second portion adjacent to the first portion; and a third portion connected to the first portion and the second portion.
摘要翻译： 根据实施例，半导体存储器件包括多个控制栅电极，半导体层和电荷累积层。 多个控制栅电极堆叠在基板上。 半导体层的一端与基板连接，具有与基板垂直的方向作为其较长方向，并面对多个控制栅电极。 电荷累积层位于控制栅电极和半导体层之间。 假设位于多个控制栅电极的最下层中的至少一个控制栅电极为第一控制栅电极，第一控制栅电极包括：第一部分; 与第一部分相邻的第二部分; 以及连接到第一部分和第二部分的第三部分。
-
10.发明授权公开(公告)号：US09312134B2
公开(公告)日：2016-04-12
申请号：US14150504
申请日：2014-01-08
发明人： Yoshiaki Fukuzumi , Ryota Katsumata , Masaru Kito , Masaru Kidoh , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Tomoko Fujiwara , Hideaki Aochi , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
IPC分类号： H01L29/792 , H01L21/223 , H01L27/115 , H01L29/66 , H01L21/265 , H01L29/78
CPC分类号： H01L27/11582 , H01L21/223 , H01L21/265 , H01L27/11578 , H01L29/04 , H01L29/1037 , H01L29/16 , H01L29/42344 , H01L29/4916 , H01L29/66666 , H01L29/66833 , H01L29/7827 , H01L29/792 , H01L29/7926
摘要： A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.
摘要翻译： 一种非易失性半导体存储器件，包括：堆叠结构单元，包括在第一方向上交替地堆叠有多个电极膜的多个绝缘膜; 选择栅极电极，其沿所述第一方向堆叠在所述层叠结构单元上; 绝缘层，其沿所述第一方向堆叠在所述选择栅电极上; 第一半导体柱在第一方向上穿透层叠结构单元，选择栅电极和绝缘层，第一半导体柱的第一截面具有环形构造，第一横截面在垂直于 第一方向 第一核心单元，其被埋在第一半导体柱的内侧，第一芯单元从绝缘层的上表面凹入; 以及设置在所述第一芯单元上以接触所述第一芯单元的所述第一半导体柱的第一导电层。
-
-
-
-
-
-
-
-
-
搜索结果
59 条记录 (耗时 0.023 秒)
