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公开(公告)号:US11621278B2
公开(公告)日:2023-04-04
申请号:US17700951
申请日:2022-03-22
申请人: KIOXIA CORPORATION
发明人: Toshifumi Minami , Atsuhiro Sato , Keisuke Yonehama , Yasuyuki Baba , Hiroshi Shinohara , Hideyuki Kamata , Teppei Higashitsuji
IPC分类号: H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L27/11578 , H01L27/11551 , H01L29/792 , H01L27/11563 , H01L27/11556
摘要: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.
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公开(公告)号:US11705204B2
公开(公告)日:2023-07-18
申请号:US17585370
申请日:2022-01-26
申请人: KIOXIA CORPORATION
发明人: Masanobu Shirakawa , Takuya Futatsuyama , Kenichi Abe , Hiroshi Nakamura , Keisuke Yonehama , Atsuhiro Sato , Hiroshi Shinohara , Yasuyuki Baba , Toshifumi Minami
IPC分类号: G11C16/00 , G11C16/14 , G11C16/04 , G11C11/56 , H10B43/27 , H10B43/35 , G11C16/08 , G11C16/10 , G11C16/26 , G11C29/42 , G11C16/34
CPC分类号: G11C16/14 , G11C11/5635 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , G11C29/42 , H10B43/27 , H10B43/35 , G11C16/3445
摘要: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.
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公开(公告)号:US11270773B2
公开(公告)日:2022-03-08
申请号:US17103504
申请日:2020-11-24
申请人: KIOXIA CORPORATION
发明人: Masanobu Shirakawa , Takuya Futatsuyama , Kenichi Abe , Hiroshi Nakamura , Keisuke Yonehama , Atsuhiro Sato , Hiroshi Shinohara , Yasuyuki Baba , Toshifumi Minami
IPC分类号: G11C16/00 , G11C16/14 , G11C16/04 , H01L27/1157 , H01L27/11582 , G11C11/56 , G11C16/08 , G11C16/10 , G11C16/26 , G11C29/42 , G11C16/34
摘要: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.
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公开(公告)号:US12022657B2
公开(公告)日:2024-06-25
申请号:US18176656
申请日:2023-03-01
申请人: KIOXIA CORPORATION
发明人: Toshifumi Minami , Atsuhiro Sato , Keisuke Yonehama , Yasuyuki Baba , Hiroshi Shinohara , Hideyuki Kamata , Teppei Higashitsuji
IPC分类号: H10B43/27 , H01L29/792 , H10B41/20 , H10B41/27 , H10B43/00 , H10B43/10 , H10B43/20 , H10B43/35
CPC分类号: H10B43/27 , H01L29/7926 , H10B41/20 , H10B41/27 , H10B43/00 , H10B43/10 , H10B43/20 , H10B43/35
摘要: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.
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公开(公告)号:US11315950B2
公开(公告)日:2022-04-26
申请号:US17021121
申请日:2020-09-15
申请人: KIOXIA CORPORATION
发明人: Toshifumi Minami , Atsuhiro Sato , Keisuke Yonehama , Yasuyuki Baba , Hiroshi Shinohara , Hideyuki Kamata , Teppei Higashitsuji
IPC分类号: H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L27/11578 , H01L27/11551 , H01L27/11563 , H01L27/11556 , H01L29/792
摘要: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.
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