公开(公告)号：US20240320091A1

公开(公告)日：2024-09-26

申请号：US18604940

申请日：2024-03-14

Applicant: Kioxia Corporation

Inventor： Ryo YAMAKI ,  Masanobu SHIRAKAWA

IPC: G06F11/10

CPC classification number: G06F11/1068 ,  G06F11/1016

Abstract: A memory system includes a memory and a memory controller. The memory controller includes an encoder including a first encoder configured to generate a first codeword from a plurality of first data sections. The first codeword includes a first error correction code parity for correcting errors in number based on a rank in the plurality of first data sections and the first codeword. The first codeword includes a plurality of first bit strings respectively associated with a plurality of columns. The first bit strings each include a plurality of bits respectively associated with a plurality of rows. The memory controller is configured to write the plurality of first bit strings into the plurality of magnetic bodies, respectively, such that the magnetic body in which one of the first bit strings is written is different.

公开(公告)号：US20210089392A1

公开(公告)日：2021-03-25

申请号：US16807220

申请日：2020-03-03

Applicant: Kioxia Corporation

Inventor： Masanobu SHIRAKAWA ,  Hideki YAMADA ,  Marie TAKADA ,  Ryo YAMAKI ,  Osamu TORII ,  Naomi TAKEDA

IPC: G06F11/10 ,  G06F9/30

Abstract: According to one embodiment, a memory system controls a shift resister memory and writes encoded data including a plurality of error correction code frames into a block of the shift resister memory. The memory system is configured to store, into a location corresponding to a first layer in a first data storing shift string, first data included in a first error correction code frame, to store, into a location corresponding to a second layer in the first data storing shift string, second data included in a second error correction code frame, and to store, into a location corresponding to the second layer in a second data storing shift string, third data included in the first error correction code frame.

公开(公告)号：US20240420778A1

公开(公告)日：2024-12-19

申请号：US18815516

申请日：2024-08-26

Applicant: Kioxia Corporation

Inventor： Tsukasa TOKUTOMI ,  Masanobu SHIRAKAWA ,  Kengo KUROSE ,  Marie TAKADA ,  Ryo YAMAKI ,  Kiyotaka IWASAKI ,  Yoshihisa KOJIMA

IPC: G11C16/26 ,  G06F3/06 ,  G06F11/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C29/52 ,  H10B43/27 ,  H10B43/35

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller is configured: to store, in a buffer, a data set read from a cell unit, and an expected data set generated by an error correction on the data set; to count a number of first and second memory cells corresponding to a first and a second combination of data in the data set and the expected data set, respectively, among the memory cells in the cell unit; to calculate a shift amount of a read voltage used in a read operation from the cell unit, based on the number of the first and second memory cells; and to apply the shift amount to a next read operation from the first cell unit.

公开(公告)号：US20220093198A1

公开(公告)日：2022-03-24

申请号：US17158161

申请日：2021-01-26

Applicant: Kioxia Corporation

Inventor： Naomi TAKEDA ,  Ryo YAMAKI ,  Masanobu SHIRAKAWA

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/40 ,  G11C29/18 ,  G11C29/12

Abstract: According to one embodiment, a memory system includes a nonvolatile memory including a plurality of cell units, each of the plurality of cell units including a plurality of memory cells, and a memory controller. The memory controller is configured to: read first data from a first cell unit, using a first correction amount of a read voltage; identify an address of an error bit in the first data; update the first correction amount to a second correction amount, based on the first data and the address of the error bit of the first data; and read second data from a second cell unit different from the first cell unit, using a third correction amount based on the second correction amount.

公开(公告)号：US20230251928A1

公开(公告)日：2023-08-10

申请号：US17895465

申请日：2022-08-25

Applicant: KIOXIA CORPORATION

Inventor： Yuki MANDAI ,  Shuou NOMURA ,  Ryo YAMAKI ,  Toshikatsu HIDA

IPC: G06F11/10 ,  G11C16/08 ,  G11C16/26

CPC classification number: G06F11/1024 ,  G11C16/08 ,  G11C16/26

Abstract: A memory system includes a nonvolatile memory including memory cells, and a memory controller. The memory controller is configured to read first data through application of a first read voltage to each of the memory cells, perform a first decoding process with respect to the first data, when the first decoding process fails, perform a tracking process. The tracking process includes reading second data indicating a threshold voltage level of each of the memory cells through application of a plurality of second read voltages to each of the memory cells, and obtaining, with respect to each of the memory cells, likelihood information using the second data. The second read voltages are shifted by a predetermined amount. The memory controller is further configured to perform a second decoding process with respect to the second data using the likelihood information.

公开(公告)号：US20210074366A1

公开(公告)日：2021-03-11

申请号：US16802477

申请日：2020-02-26

Applicant: KIOXIA CORPORATION

Inventor： Koji HORISAKI ,  Kazuhisa HORIUCHI ,  Ryo YAMAKI ,  Gibeom PARK ,  Youyang NG

IPC: G11C16/26 ,  G11C16/12 ,  G11C16/34 ,  G06F13/16

Abstract: A memory controller performs a reference read on a plurality of memory cells using reference read voltages, generates a histogram indicating the number of memory cells in different threshold voltage bins based on results of the reference read, estimates actual read voltages based on the histogram and a first estimation function, and reads data using the actual read voltages. When reading of the data with the actual read voltages estimated using the first estimation function fails, the memory controller estimates actual read voltages using a second estimation function different from the first estimation function and reads the data with the actual read voltages estimated using the second estimation function.

公开(公告)号：US20250022498A1

公开(公告)日：2025-01-16

申请号：US18764581

申请日：2024-07-05

Applicant: Kioxia Corporation

Inventor： Shogo MUTO ,  Masanobu SHIRAKAWA ,  Hideki YAMADA ,  Ryo YAMAKI ,  Yoshihiro UEDA ,  Tsuyoshi KONDO

IPC: G11C11/16 ,  G11C19/08 ,  H10B61/00 ,  H10N50/10

Abstract: A first circuit outputs first information indicating presence/absence of a magnetic wall between two adjacent portions among portions of a magnetic body, and second information based on the combination of magnetization states of the two portions. A first storage circuit stores first bits corresponding to the portions. A most significant bit of the first bits has a value independent of a magnetization state of a corresponding one of the portions, and the first bits have a value based on the first information. A second storage circuit stores the second information. The second circuit causes the first storage circuit to output the first bits when a value of a least significant bit of the first bits matches a value of the second information, and otherwise third bits having inverse values of the first bits.

公开(公告)号：US20210295943A1

公开(公告)日：2021-09-23

申请号：US17010041

申请日：2020-09-02

Applicant: Kioxia Corporation

Inventor： Ryo YAMAKI ,  Yuki KOMATSU

IPC: G11C29/44 ,  G11C29/52 ,  G11C29/50 ,  G06F11/07

Abstract: A memory system includes a non-volatile memory and a controller configured to divides an n-dimensional space into a plurality of regions by a plurality of hyperplanes, assign a representative point of a read level for reading data from a plurality of memory cells to each region, trace a branch node in the binary tree by determining whether a first read level is higher or lower than a voltage level at the branch node of the binary tree, determine a read level of a representative point assigned to a region correlated with a leaf node among the plurality of divided regions as a second read level corresponding to the first read level when reaching the leaf node of the binary tree by tracing the branch node in the binary tree, and cause the memory to read data of the cells by applying a voltage of the second read level.

公开(公告)号：US20240055065A1

公开(公告)日：2024-02-15

申请号：US18230151

申请日：2023-08-03

Applicant: Kioxia Corporation

Inventor： Ryo YAMAKI ,  Masanobu SHIRAKAWA ,  Naomi TAKEDA ,  Takashi NAKAGAWA ,  Shingo YANAGAWA

IPC: G11C29/12

CPC classification number: G11C29/12005 ,  G11C2029/1202

Abstract: According to one embodiment, a memory system includes a non-volatile first memory with first storage areas. A controller executes a first read operation on a second storage area of the first storage areas. When an error correction in the first read operation fails, the controller acquires a first measured value being a value of a read voltage for suppressing the number of occurrences of error bits in the second storage area. The controller updates, on the basis of the first measured value, one of first candidate values of the read voltage with a second candidate value. When the error correction in a second read operation for a third storage area of the first storage areas fails, the controller executes the read operation once or more on the third storage area by using, as the read voltages, different first candidate values of the first candidate values.

公开(公告)号：US20230420067A1

公开(公告)日：2023-12-28

申请号：US18053896

申请日：2022-11-09

Applicant: Kioxia Corporation

Inventor： Marie TAKADA ,  Masanobu SHIRAKAWA ,  Hideki YAMADA ,  Ryo YAMAKI

IPC: G11C29/52 ,  G11C11/4096 ,  G11C11/4074

CPC classification number: G11C29/52 ,  G11C11/4096 ,  G11C11/4074

Abstract: A memory system includes a nonvolatile memory including memory cells each configured to store first and second bits, and a memory controller. The memory controller is configured to: read first data by using a first voltage to a first read process that reads data corresponding to the first bit from the memory cells; read second data by using a second voltage to a second read process that reads data corresponding to the second bit from the memory cells; in a case where an error correction process of the first data is successful, determine a third voltage, based on the first data and third data that is obtained by error-correcting the first data; and update a first read voltage that is used to the first read process, from the first voltage to the third voltage.