公开(公告)号：US12165712B2

公开(公告)日：2024-12-10

申请号：US18362221

申请日：2023-07-31

Applicant: KIOXIA CORPORATION

Inventor： Tsukasa Tokutomi ,  Masanobu Shirakawa ,  Marie Takada ,  Shohei Asami ,  Masamichi Fujiwara

IPC: G11C16/26 ,  G06F3/06 ,  G11C16/04 ,  G11C11/56 ,  G11C16/08 ,  H10B43/27 ,  H10B43/35

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.

公开(公告)号：US12029031B2

公开(公告)日：2024-07-02

申请号：US18314527

申请日：2023-05-09

Applicant: KIOXIA CORPORATION

Inventor： Takehiko Amaki ,  Yoshihisa Kojima ,  Toshikatsu Hida ,  Marie Grace Izabelle Angeles Sia ,  Riki Suzuki ,  Shohei Asami

IPC: H10B41/27 ,  G11C7/04 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/107 ,  G11C16/16 ,  G11C16/26 ,  H10B43/27 ,  H10B43/35

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.

公开(公告)号：US11763893B2

公开(公告)日：2023-09-19

申请号：US17568336

申请日：2022-01-04

Applicant: Kioxia Corporation

Inventor： Tsukasa Tokutomi ,  Masanobu Shirakawa ,  Marie Takada ,  Shohei Asami ,  Masamichi Fujiwara

IPC: G11C16/26 ,  G11C16/04 ,  G06F3/06 ,  G11C16/08 ,  G11C11/56 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/26 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/0483 ,  G11C11/5671 ,  G11C16/08 ,  H10B43/27 ,  H10B43/35

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.

公开(公告)号：US11710515B2

公开(公告)日：2023-07-25

申请号：US17888065

申请日：2022-08-15

Applicant: Kioxia Corporation

Inventor： Shohei Asami ,  Toshikatsu Hida ,  Riki Suzuki

IPC: G11C11/40 ,  G11C11/406 ,  G11C16/16 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C11/40626 ,  G11C11/40615 ,  G11C16/102 ,  G11C16/16 ,  G11C16/3495

Abstract: According to one embodiment, a memory system includes a non-volatile memory and a memory controller. The non-volatile memory includes a plurality of groups, each including a plurality of memory cells. The memory controller is configured to determine whether to execute a refresh process for a first group based on whether a first temperature in a write process for the first group and a second temperature after the write process for the first group satisfy a first condition.

公开(公告)号：US11696441B2

公开(公告)日：2023-07-04

申请号：US17725638

申请日：2022-04-21

Applicant: Kioxia Corporation

Inventor： Takehiko Amaki ,  Yoshihisa Kojima ,  Toshikatsu Hida ,  Marie Grace Izabelle Angeles Sia ,  Riki Suzuki ,  Shohei Asami

IPC: G11C16/08 ,  H10B41/27 ,  G11C16/10 ,  G11C16/04 ,  G11C16/16 ,  G11C7/04 ,  G11C16/26 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/107 ,  G11C16/16 ,  G11C16/26 ,  H10B43/27 ,  H10B43/35

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.

公开(公告)号：US11462256B2

公开(公告)日：2022-10-04

申请号：US17349248

申请日：2021-06-16

Applicant: Kioxia Corporation

Inventor： Shohei Asami ,  Toshikatsu Hida ,  Riki Suzuki

IPC: G11C11/40 ,  G11C11/406 ,  G11C16/16 ,  G11C16/10 ,  G11C16/34

Abstract: According to one embodiment, a memory system includes a non-volatile memory and a memory controller. The non-volatile memory includes a plurality of groups, each including a plurality of memory cells. The memory controller is configured to determine whether to execute a refresh process for a first group based on whether a first temperature in a write process for the first group and a second temperature after the write process for the first group satisfy a first condition.

公开(公告)号：US11309051B2

公开(公告)日：2022-04-19

申请号：US17022274

申请日：2020-09-16

Applicant: Kioxia Corporation

Inventor： Shohei Asami ,  Takehiko Amaki

IPC: G11C16/06 ,  G11C29/42 ,  G11C29/44 ,  G11C29/12 ,  G11C16/10 ,  G11C16/26 ,  G11C16/04 ,  G11C29/50

Abstract: According to one embodiment, a memory system includes: a memory chip including a first memory block and first word lines, the first memory block including a first memory string which includes first memory cells that are coupled in series, the first word lines being respectively coupled to gates of the first memory cells; a memory controller coupled to an external device, controlling the memory chip, and capable of performing an error checking and correcting process of data. When a write instruction is received from the external device, the memory controller is configured to perform a write operation on a second memory cell which is one of the first memory cells, and to perform a read verify operation including a read process and the ECC process on a third memory cell which is one of the first memory cells.