公开(公告)号：US06967131B2

公开(公告)日：2005-11-22

申请号：US10694793

申请日：2003-10-29

申请人： Katherine L. Saenger ,  Cyril Cabral, Jr. ,  Emanuel I. Cooper ,  Hariklia Deligianni ,  Panayotis Andricacos ,  Philippe M. Vereecken

发明人： Katherine L. Saenger ,  Cyril Cabral, Jr. ,  Emanuel I. Cooper ,  Hariklia Deligianni ,  Panayotis Andricacos ,  Philippe M. Vereecken

IPC分类号： H01L21/28 ,  H01L21/288 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8283

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/66621 ,  H01L29/7834

摘要： Disclosed is a method for making a metal gate for a FET, wherein the metal gate comprises at least some material deposited by electroplating as well as an FET device comprising a metal gate that is at least partially plated. Further disclosed is a method for making a metal gate for a FET wherein the metal gate comprises at least some plated material and the method comprises the steps of: selecting a substrate having a top surface and a recessed region; conformally depositing a thin conductive seed layer on the substrate; and electroplating a filler gate metal on the seed layer to fill and overfill the recessed region.

公开(公告)号：US07868410B2

公开(公告)日：2011-01-11

申请号：US12040350

申请日：2008-02-29

申请人： Philippe M. Vereecken ,  Veeraraghavan S. Basker ,  Cyril Cabral, Jr. ,  Emanuel I. Cooper ,  Hariklia Deligianni ,  Martin M. Frank ,  Rajarao Jammy ,  Vamsi Krishna Paruchuri ,  Katherine L. Saenger ,  Xiaoyan Shao

发明人： Philippe M. Vereecken ,  Veeraraghavan S. Basker ,  Cyril Cabral, Jr. ,  Emanuel I. Cooper ,  Hariklia Deligianni ,  Martin M. Frank ,  Rajarao Jammy ,  Vamsi Krishna Paruchuri ,  Katherine L. Saenger ,  Xiaoyan Shao

IPC分类号： H01L21/70

CPC分类号： H01L21/2885 ,  C25D3/50 ,  C25D5/02 ,  C25D5/024 ,  C25D5/54 ,  C25D7/123 ,  C25D9/04 ,  C25F3/14 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/76885 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78648

摘要： A method is provided for electroplating a gate metal or other conducting or semiconducting material directly on a dielectric such as a gate dielectric. The method involves selecting a substrate, dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt allow an electrochemical current to be passed from the substrate through the dielectric layer into the electrolyte solution or melt. Methods are also provided for electrochemical modification of dielectrics utilizing through-dielectric current flow.

摘要翻译： 提供了一种用于将栅极金属或其它导电或半导体材料直接电镀在诸如栅极电介质的电介质上的方法。 该方法包括选择衬底，电介质层和电解质溶液或熔体，其中衬底，电介质层和电解质溶液或熔体的组合允许电化学电流从衬底通过电介质层进入电解质溶液或 熔化。 还提供了利用电介质电流流动的电介质电化学修饰方法。

公开(公告)号：US07368045B2

公开(公告)日：2008-05-06

申请号：US11050790

申请日：2005-01-27

申请人： Philippe M. Vereecken ,  Veeraraghavan S. Basker ,  Cyril Cabral, Jr. ,  Emanuel I. Cooper ,  Hariklia Deligianni ,  Martin M. Frank ,  Rajarao Jammy ,  Vamsi Krishna Paruchuri ,  Katherine L. Saenger ,  Xiaoyan Shao

发明人： Philippe M. Vereecken ,  Veeraraghavan S. Basker ,  Cyril Cabral, Jr. ,  Emanuel I. Cooper ,  Hariklia Deligianni ,  Martin M. Frank ,  Rajarao Jammy ,  Vamsi Krishna Paruchuri ,  Katherine L. Saenger ,  Xiaoyan Shao

IPC分类号： C25D5/02 ,  C25D11/04

CPC分类号： H01L21/2885 ,  C25D3/50 ,  C25D5/02 ,  C25D5/024 ,  C25D5/54 ,  C25D7/123 ,  C25D9/04 ,  C25F3/14 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/76885 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78648

摘要： A method is provided for electroplating a gate metal or other conducting or semiconducting material directly on a dielectric such as a gate dielectric. The method involves selecting a substrate, dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt allow an electrochemical current to be passed from the substrate through the dielectric layer into the electrolyte solution or melt. Methods are also provided for electrochemical modification of dielectrics utilizing through-dielectric current flow.

摘要翻译： 提供了一种用于将栅极金属或其它导电或半导体材料直接电镀在诸如栅极电介质的电介质上的方法。 该方法包括选择衬底，电介质层和电解质溶液或熔体，其中衬底，电介质层和电解质溶液或熔体的组合允许电化学电流从衬底通过电介质层进入电解质溶液或 熔化。 还提供了利用电介质电流流动的电介质电化学修饰方法。

公开(公告)号：US20080142894A1

公开(公告)日：2008-06-19

申请号：US12040350

申请日：2008-02-29

申请人： Philippe M. Vereecken ,  Veeraraghavan S. Basker ,  Cyril Cabral ,  Emanuel I. Cooper ,  Hariklia Deligianni ,  Martin M. Frank ,  Rajarao Jammy ,  Vamsi Krishna Paruchuri ,  Katherine L. Saenger ,  Xiaoyan Shao

发明人： Philippe M. Vereecken ,  Veeraraghavan S. Basker ,  Cyril Cabral ,  Emanuel I. Cooper ,  Hariklia Deligianni ,  Martin M. Frank ,  Rajarao Jammy ,  Vamsi Krishna Paruchuri ,  Katherine L. Saenger ,  Xiaoyan Shao

IPC分类号： H01L27/088 ,  H01L29/423

CPC分类号： H01L21/2885 ,  C25D3/50 ,  C25D5/02 ,  C25D5/024 ,  C25D5/54 ,  C25D7/123 ,  C25D9/04 ,  C25F3/14 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/76885 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78648

摘要： A method is provided for electroplating a gate metal or other conducting or semiconducting material directly on a dielectric such as a gate dielectric. The method involves selecting a substrate, dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt allow an electrochemical current to be passed from the substrate through the dielectric layer into the electrolyte solution or melt. Methods are also provided for electrochemical modification of dielectrics utilizing through-dielectric current flow.

摘要翻译： 提供了一种用于将栅极金属或其它导电或半导体材料直接电镀在诸如栅极电介质的电介质上的方法。 该方法包括选择衬底，电介质层和电解质溶液或熔体，其中衬底，电介质层和电解质溶液或熔体的组合允许电化学电流从衬底通过电介质层进入电解质溶液或 熔化。 还提供了利用电介质电流流动的电介质电化学修饰方法。

公开(公告)号：US07667278B2

公开(公告)日：2010-02-23

申请号：US11372140

申请日：2006-03-10

申请人： Cyril Cabral, Jr. ,  Christophe Detavernier ,  Rajarao Jammy ,  Katherine L. Saenger

发明人： Cyril Cabral, Jr. ,  Christophe Detavernier ,  Rajarao Jammy ,  Katherine L. Saenger

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/06 ,  H01L29/12

CPC分类号： H01L29/4966 ,  H01L21/823842

摘要： A semiconductor device such as a complementary metal oxide semiconductor (CMOS) including at least one FET that includes a gate electrode including a metal carbide and method of fabrication are provided. The CMOS comprises dual work function metal gate electrodes whereby the dual work functions are provided by a metal and a carbide of a metal.

摘要翻译： 提供了包括包括包括金属碳化物的栅电极和至少一种制造方法的至少一个FET的互补金属氧化物半导体（CMOS）的半导体器件。 CMOS包括双功能金属栅电极，由此双功能功能由金属和金属的碳化物提供。

公开(公告)号：US06187679B1

公开(公告)日：2001-02-13

申请号：US08807739

申请日：1997-02-26

申请人： Cyril Cabral, Jr. ,  Lawrence Alfred Clevenger ,  Francois Max d'Heurle ,  James McKell Edwin Harper ,  Randy William Mann ,  Glen Lester Miles ,  James Spiros Nakos ,  Ronnen Andrew Roy ,  Katherine L. Saenger

发明人： Cyril Cabral, Jr. ,  Lawrence Alfred Clevenger ,  Francois Max d'Heurle ,  James McKell Edwin Harper ,  Randy William Mann ,  Glen Lester Miles ,  James Spiros Nakos ,  Ronnen Andrew Roy ,  Katherine L. Saenger

IPC分类号： H01L2144

CPC分类号： C30B1/02 ,  C30B29/10 ,  H01L21/28518 ,  H01L29/665

摘要： Low resistivity titanium silicide, and semiconductor devices incorporating the same, may be formed by titanium alloy comprising titanium and 1-20 atomic percent refractory metal deposited in a layer overlying a silicon substrate, the substrate is then heated to a temperature sufficient to substantially form C54 phase titanium silicide. The titanium alloy may further comprise silicon and the refractory metal may be Mo, W, Ta, Nb, V, or Cr, and more preferably is Ta or Nb. The heating step used to form the low resistivity titanium silicide is performed at a temperature less than 900° C., and more preferably between about 600-700° C.

摘要翻译： 低电阻率钛硅化物和包含该低电阻率钛硅化物的半导体器件可以由在钛硅衬底上沉积的钛和1-20原子百分比的难熔金属的钛合金形成，然后将衬底加热至足以基本形成C54 相钛硅化物。 钛合金还可以包含硅，难熔金属可以是Mo，W，Ta，Nb，V或Cr，更优选是Ta或Nb。 用于形成低电阻率硅化钛的加热步骤在低于900℃的温度下进行，更优选在约600-700℃之间

公开(公告)号：US5828131A

公开(公告)日：1998-10-27

申请号：US586046

申请日：1996-01-16

申请人： Cyril Cabral, Jr. ,  Lawrence Alfred Clevenger ,  Francois Max d'Heurle ,  James McKell Edwin Harper ,  Randy William Mann ,  Glen Lester Miles ,  James Spiros Nakos ,  Ronnen Andrew Roy ,  Katherine L. Saenger

发明人： Cyril Cabral, Jr. ,  Lawrence Alfred Clevenger ,  Francois Max d'Heurle ,  James McKell Edwin Harper ,  Randy William Mann ,  Glen Lester Miles ,  James Spiros Nakos ,  Ronnen Andrew Roy ,  Katherine L. Saenger

IPC分类号： C23C20/02 ,  C30B1/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/45

CPC分类号： C30B1/02 ,  C30B29/10 ,  H01L21/28518 ,  H01L29/665

摘要： Low resistivity titanium silicide, and semiconductor devices incorporating the same, may be formed by titanium alloy comprising titanium and 1-20 atomic percent refractory metal deposited in a layer overlying a silicon substrate, the substrate is then heated to a temperature sufficient to substantially form C54 phase titanium silicide. The titanium alloy may further comprise silicon and the refractory metal may be Mo, W, Ta, Nb, V, or Cr, and more preferably is Ta or Nb. The heating step used to form the low resistivity titanium silicide is performed at a temperature less than 900.degree. C., and more preferably between about 600.degree.-700.degree. C.

摘要翻译： 低电阻率钛硅化物和包含该低电阻率钛硅化物的半导体器件可以由在钛硅衬底上沉积的钛和1-20原子百分比的难熔金属的钛合金形成，然后将衬底加热至足以基本形成C54 相钛硅化物。 钛合金还可以包含硅，难熔金属可以是Mo，W，Ta，Nb，V或Cr，更优选是Ta或Nb。 用于形成低电阻率硅化钛的加热步骤在低于900℃的温度下进行，更优选在约600℃至700℃之间。

公开(公告)号：US07785982B2

公开(公告)日：2010-08-31

申请号：US11620224

申请日：2007-01-05

申请人： Stephen W. Bedell ,  Hariklia Deligianni ,  Qiang Huang ,  Lubomyr T. Romankiw ,  Devendra K. Sadana ,  Katherine L. Saenger

发明人： Stephen W. Bedell ,  Hariklia Deligianni ,  Qiang Huang ,  Lubomyr T. Romankiw ,  Devendra K. Sadana ,  Katherine L. Saenger

IPC分类号： H01L21/76

CPC分类号： H01L21/823807 ,  H01L21/0237 ,  H01L21/02532 ,  H01L21/02628 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/28255 ,  H01L29/1054 ,  H01L29/78

摘要： Methods for electrodepositing germanium on various semiconductor substrates such as Si, Ge, SiGe, and GaAs are provided. The electrodeposited germanium can be formed as a blanket or patterned film, and may be crystallized by solid phase epitaxy to the orientation of the underlying semiconductor substrate by subsequent annealing. These plated germanium layers may be used as the channel regions of high-mobility channel field effect transistors (FETs) in complementary metal oxide semiconductor (CMOS) circuits.

摘要翻译： 提供了在诸如Si，Ge，SiGe和GaAs的各种半导体衬底上电沉积锗的方法。 电沉积锗可以形成为覆盖或图案化的膜，并且可以通过后续退火使固相外延结晶到下面的半导体衬底的取向。 这些电镀锗层可以用作互补金属氧化物半导体（CMOS）电路中的高迁移率沟道场效应晶体管（FET）的沟道区。

公开(公告)号：US07064050B2

公开(公告)日：2006-06-20

申请号：US10722557

申请日：2003-11-28

申请人： Cyril Cabral, Jr. ,  Christophe Detavernier ,  Rajarao Jammy ,  Katherine L. Saenger

发明人： Cyril Cabral, Jr. ,  Christophe Detavernier ,  Rajarao Jammy ,  Katherine L. Saenger

IPC分类号： H01L21/3205

CPC分类号： H01L29/4966 ,  H01L21/823842

摘要： A semiconductor device such as a complementary metal oxide semiconductor (CMOS) comprising at least one FET that comprises a gate electrode comprising a metal carbide and method of fabrication are provided. The CMOS comprises dual work function metal gate electrodes whereby the dual work functions are provided by a metal and a carbide of a metal.

摘要翻译： 提供了包括至少一个FET的半导体器件，例如互补金属氧化物半导体（CMOS），其包括包含金属碳化物的栅电极和制造方法。 CMOS包括双功能金属栅电极，由此双功能功能由金属和金属的碳化物提供。

公开(公告)号：US20090302353A1

公开(公告)日：2009-12-10

申请号：US12541499

申请日：2009-08-14

申请人： Stephen W. Bedell ,  Hariklia Deligianni ,  Qiang Huang ,  Lubomyr T. Romankiw ,  Devendra K. Sadana ,  Katherine L. Saenger

发明人： Stephen W. Bedell ,  Hariklia Deligianni ,  Qiang Huang ,  Lubomyr T. Romankiw ,  Devendra K. Sadana ,  Katherine L. Saenger

IPC分类号： H01L29/165 ,  H01L29/16 ,  H01L29/78 ,  H01L27/092 ,  H01L29/12

CPC分类号： H01L21/823807 ,  H01L21/0237 ,  H01L21/02532 ,  H01L21/02628 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/28255 ,  H01L29/1054 ,  H01L29/78

摘要： Methods for electrodepositing germanium on various semiconductor substrates such as Si, Ge, SiGe, and GaAs are provided. The electrodeposited germanium can be formed as a blanket or patterned film, and may be crystallized by solid phase epitaxy to the orientation of the underlying semiconductor substrate by subsequent annealing. These plated germanium layers may be used as the channel regions of high-mobility channel field effect transistors (FETs) in complementary metal oxide semiconductor (CMOS) circuits.

摘要翻译： 提供了在诸如Si，Ge，SiGe和GaAs的各种半导体衬底上电沉积锗的方法。 电沉积锗可以形成为覆盖或图案化的膜，并且可以通过后续退火使固相外延结晶到下面的半导体衬底的取向。 这些电镀锗层可以用作互补金属氧化物半导体（CMOS）电路中的高迁移率沟道场效应晶体管（FET）的沟道区。