公开(公告)号：US4933907A

公开(公告)日：1990-06-12

申请号：US278552

申请日：1988-12-01

申请人： Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Hiroyuki Yamasaki ,  Takahiro Komatsu ,  Yoichi Tobita

发明人： Masaki Kumanoya ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Hiroyuki Yamasaki ,  Takahiro Komatsu ,  Yoichi Tobita

IPC分类号： G11C11/406

CPC分类号： G11C11/40615 ,  G11C11/406

摘要： A dynamic random access memory having a self-refresh mode comprises a memory array partitioned into four groups in which control are respectively performed and a partial activation control circuit. The four groups in the memory array are alternately refreshed two by two in an operation under the self-refresh mode. As a result, each group in the memory array is refreshed at a time interval of two times a conventional refresh interval, so that the power consumption is decreased.

摘要翻译： 具有自刷新模式的动态随机存取存储器包括分为四组的存储器阵列，其中分别执行控制和部分激活控制电路。 存储器阵列中的四组在自刷新模式下的操作中被两个两个地刷新。 结果，存储器阵列中的每个组以传统刷新间隔的两倍的时间间隔被刷新，使得功耗降低。

公开(公告)号：US4907199A

公开(公告)日：1990-03-06

申请号：US271489

申请日：1988-11-15

申请人： Katsumi Dosaka ,  Masaki Kumanoya ,  Yasuhiro Konishi ,  Hiroyuki Yamasaki ,  Takahiro Komatsu

发明人： Katsumi Dosaka ,  Masaki Kumanoya ,  Yasuhiro Konishi ,  Hiroyuki Yamasaki ,  Takahiro Komatsu

IPC分类号： G11C11/409 ,  G11C11/403 ,  G11C11/406 ,  G11C11/4094

CPC分类号： G11C11/4094 ,  G11C11/406

摘要： A dynamic semiconductor memory device is divided into a plurality of blocks. An operation of the semiconductor memory device is in either of a normal mode and a refresh mode, depending on the level of a refresh signal. In the normal mode, at an off time period, a potential on a bit line pair is equalized and a precharge potential is applied to the bit line pair. At the access time, equalizing of the potential on the bit line pair and supply of the precharge potential are stopped in a selected block and then, a word line driving signal is raised. On the other hand, in the refresh mode, at the off time period, the potential on the bit line pair is held at "H" and "L" levels by a sense amplifier, so that the potential on the bit line pair is not equalized and the precharge potential is not supplied. On this occasion, a precharge potential generating circuit is electrically disconnected from a power supply. At the time of refresh operation, the sense amplifier is rendered inactive in the selected block, so that the potential on the bit line pair is equalized and then, the word line driving signal is raised.

摘要翻译： 动态半导体存储器件被分成多个块。 根据刷新信号的电平，半导体存储器件的操作是正常模式和刷新模式。 在正常模式下，在关闭时间段，位线对上的电位被均衡，并且预充电电位被施加到位线对。 在访问时间，在所选择的块中停止位线对上的电位的均衡和预充电电势的供给，然后提高字线驱动信号。 另一方面，在刷新模式下，在关闭时间段，位线对上的电位由读出放大器保持在“H”和“L”电平，使得位线对上的电位不是 均衡，不提供预充电电位。 在这种情况下，预充电电位产生电路与电源电气断开。 在刷新操作时，读出放大器在所选择的块中变为无效，使位线对上的电位相等，然后提高字线驱动信号。

公开(公告)号：US4954992A

公开(公告)日：1990-09-04

申请号：US269757

申请日：1988-11-08

申请人： Masaki Kumanoya ,  Hirofumi Shinohara ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Takahiro Komatsu ,  Hiroyuki Yamasaki

发明人： Masaki Kumanoya ,  Hirofumi Shinohara ,  Katsumi Dosaka ,  Yasuhiro Konishi ,  Takahiro Komatsu ,  Hiroyuki Yamasaki

IPC分类号： G11C7/06 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/4096

CPC分类号： G11C7/1057 ,  G11C11/4091 ,  G11C11/4096 ,  G11C7/062 ,  G11C7/065 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1069

摘要： A dynamic random access memory device includes a pair of write-in data transferring buses for transferring data to be written, a pair of read-out data transferring buses for transferring data to be read provided additionally and separately from the write-in data transferring bus pair and a plurality of current mirror type sense amplifiers formed of CMOS transistors and each amplifier being provided between a bit line pair and the read-out data transferring bus pair and having input nodes connected to the corresponding bit line pair and the read-out data transferring bus pair forming output nodes thereof. The current mirror type sense amplifiers of CMOS transistors are activated in response to an output of a column decoder at earlier time than the time when conventional flip-flop type sense amplifiers are activated.

摘要翻译： 一种动态随机存取存储器件包括一对写入数据传送总线，用于传送要被写入的数据，一对读出数据传输总线，用于传送要被读取的数据，附加地和独立于写入数据传输总线 对和由CMOS晶体管形成的多个电流镜型读出放大器，并且每个放大器设置在位线对和读出数据传输总线对之间，并且具有连接到相应位线对和读出数据的输入节点 传输总线对形成其输出节点。 响应于比传统的触发器型读出放大器被激活的时间早的列解码器的输出，CMOS晶体管的电流镜式读出放大器被激活。

公开(公告)号：US4843596A

公开(公告)日：1989-06-27

申请号：US124554

申请日：1987-11-24

申请人： Hideshi Miyatake ,  Masaki Kumanoya ,  Hideto Hidaka ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Hiroyuki Yamasaki ,  Masaki Shimoda ,  Yuto Ikeda ,  Kazuhiro Tsukamoto

发明人： Hideshi Miyatake ,  Masaki Kumanoya ,  Hideto Hidaka ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Hiroyuki Yamasaki ,  Masaki Shimoda ,  Yuto Ikeda ,  Kazuhiro Tsukamoto

IPC分类号： G11C11/401 ,  G11C7/22 ,  G11C8/18

CPC分类号： G11C8/18 ,  G11C7/22

摘要： A novel semiconductor memory device includes an address detection circuit that produces a short-width pulse in response to the detection of an address change. A column decoder-activating signal generator detects the start of the short-width pulse and in response generates a column decoder-activating signal. A second detection circuit detects the conclusion of the short-width pulse and generates a second pulse that triggers a preamplifier-activating signal that activates a preamplifier and latches the data that is present on the input/output line. A reset signal generator produces a reset signal to deactivate the column decoder-activating signal and to delay the preamplifier-activating signal. The preamplifier-activating signal generator and the reset signal generator are reset while the first pulse is output.

摘要翻译： 一种新颖的半导体存储器件包括响应于地址变化的检测而产生短宽度脉冲的地址检测电路。 列解码器激活信号发生器检测短宽度脉冲的开始，并且响应于产生列解码器激活信号。 第二检测电路检测短宽度脉冲的结论，并产生触发前置放大器激活信号的第二脉冲，其激活前置放大器并锁存输入/输出线上存在的数据。 复位信号发生器产生复位信号以停用列解码器激活信号并延迟前置放大器激活信号。 当输出第一个脉冲时，前置放大器激活信号发生器和复位信号发生器被复位。

公开(公告)号：US4823322A

公开(公告)日：1989-04-18

申请号：US102683

申请日：1987-09-30

申请人： Hideshi Miyatake ,  Masaki Kumanoya ,  Hideto Hidaka ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Hiroyuki Yamasaki ,  Masaki Shimoda ,  Yuto Ikeda ,  Kazuhiro Tsukamoto

发明人： Hideshi Miyatake ,  Masaki Kumanoya ,  Hideto Hidaka ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Hiroyuki Yamasaki ,  Masaki Shimoda ,  Yuto Ikeda ,  Kazuhiro Tsukamoto

IPC分类号： G11C11/407 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/413 ,  G11C7/00

CPC分类号： G11C11/4076

摘要： A dynamic random access memory device having an input/output load connected between a pair of input/output lines and a control circuit used to generate an internal /RAS signal having a reset transition delayed with respect to the same transition of the external /RAS signal. The internal /RAS signal controls at least a word signal applied to a transistor of a selected memory cell and an enable signal applied to an enable transistor, whereby the time the transistor of the memory cell and the enable transistor become non-conductive is delayed with respect to the time at which a transfer transistor connected between each pair of bit lines and the input/output lines becomes non-conductive.

摘要翻译： 具有连接在一对输入/输出线之间的输入/输出负载和用于产生内部/ RAS信号的动态随机存取存储器件，该内部/ RAS信号具有相对于外部/ RAS信号的相同转变延迟的复位转变 。 内部/ RAS信号至少控制施加到所选择的存储单元的晶体管的字信号和施加到使能晶体管的使能信号，从而使存储器单元和使能晶体管变为不导通的时间被延迟 相对于连接在每对位线和输入/输出线之间的传输晶体管的时间变得不导通。

公开(公告)号：US4837747A

公开(公告)日：1989-06-06

申请号：US126349

申请日：1987-11-30

申请人： Katsumi Dosaka ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Yasuhiro Konishi ,  Hiroyuki Yamasaki ,  Yuto Ikeda ,  Kazuhiro Tsukamoto ,  Masaki Shimoda

发明人： Katsumi Dosaka ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Yasuhiro Konishi ,  Hiroyuki Yamasaki ,  Yuto Ikeda ,  Kazuhiro Tsukamoto ,  Masaki Shimoda

IPC分类号： G11C8/12 ,  G11C29/00

CPC分类号： G11C29/806 ,  G11C8/12

摘要： A memory cell array is divided into four blocks #1 to #4. The blocks #1 and #3 are operated when a row address signal RA.sub.8 equals "0". The blocks #2 and #4 are operated when the row address signal RA.sub.8 equals "1". A spare row sub-decoder is provided in each of the blocks. Spare row sub-decoders in the blocks #1 and #2 are connected to a spare row main decoder through a single spare decoder selecting line. The spare row sub-decoders in the blocks #2 and #4 are connected to the other spare row main decoder through another spare decoder selecting line. The spare main decoders are responsive to the row address signal RA.sub.8 and row address signals RA.sub.2, RA.sub.2, . . . , RA.sub.7, RA.sub.7 for operating a spare row sub-decoder in a block which is in the operating state.

摘要翻译： 存储单元阵列被分成四个块＃1到＃4。 当行地址信号RA8等于“0”时，块＃1和＃3被操作。 当行地址信号RA8等于“1”时，块＃2和＃4被操作。 在每个块中提供备用行子解码器。 块＃1和＃2中的备用行子解码器通过单个备用解码器选择线连接到备用主主解码器。 块＃2和＃4中的备用行子解码器通过另一个备用解码器选择线连接到另一备用行主解码器。 备用主解码器响应于行地址信号RA8和行地址信号RA2，RA2。 。 。 ，RA7，RA7，用于在处于操作状态的块中操作备用行子解码器。

公开(公告)号：US5079748A

公开(公告)日：1992-01-07

申请号：US469125

申请日：1990-01-24

申请人： Hideshi Miyatake ,  Masaki Kumanoya ,  Hideto Hidaka ,  Hiroyuki Yamasaki ,  Yasuhiro Konishi ,  Yuto Ikeda

发明人： Hideshi Miyatake ,  Masaki Kumanoya ,  Hideto Hidaka ,  Hiroyuki Yamasaki ,  Yasuhiro Konishi ,  Yuto Ikeda

IPC分类号： G11C11/409 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/417 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： G11C11/4076

摘要： A semiconductor dynamic RAM provided with an I/O load (5) rendered inactive during a writing cycle comprises a monostable multivibrator (16) for receiving a read/write indicating signal W for indicating reading and writing data from and into a memory cell (2) and outputting a signal We having a shorter duration than that of the signal W at down edge of the signal W as a trigger. The output signal We of the monostable multivibrator (16) is supplied as a control signal for rendering the I/O load (5) inactive.

公开(公告)号：US4984206A

公开(公告)日：1991-01-08

申请号：US372441

申请日：1989-06-27

申请人： Takahiro Komatsu ,  Hiroyuki Yamasaki ,  Katsumi Dosaka ,  Yoichi Tobita

发明人： Takahiro Komatsu ,  Hiroyuki Yamasaki ,  Katsumi Dosaka ,  Yoichi Tobita

IPC分类号： G11C11/409 ,  G11C7/00 ,  G11C7/06 ,  G11C7/10

CPC分类号： G11C7/1069 ,  G11C7/00 ,  G11C7/062 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1078

摘要： A dynamic random access memory comprises a pair of write-in data transferring lines (IL, IL), a pair of read-out data transferring lines (OL, OL) and a current-mirror type sense amplifier comprising (30) CMOS transistors. The current-mirror type amplifier (30) is connected between a plurality of bit line pairs (BL, BL) and the pair of read-out data transferring lines (OL, OL). At the time of data reading, the pair of write-in data transferring lines (IL, IL) is connected to the corresponding bit line pair (BL, BL) in response to a write-in column decoded signal (YW) obtained by ANDing a column decoded signal (CA) with a write-in instruction signal (W).

摘要翻译： 动态随机存取存储器包括一对写入数据传输线（IL，＆amp; Upbar＆I），一对读出数据传输线（OL，＆amp; upbar＆O）和电流镜型读出放大器，包括（30）CMOS 晶体管。 电流镜式放大器（30）连接在多个位线对（BL，＆amp; B和B）与一对读出数据传输线（OL，＆amp; upbar＆O）之间。 在数据读取时，响应于获得的写入列解码信号（YW），一对写入数据传输线（IL，＆amp; upbar＆I）被连接到对应的位线对（BL，＆amp; B和B） 通过将列解码信号（CA）与写入指令信号（W）进行AND运算。

公开(公告)号：US4945517A

公开(公告)日：1990-07-31

申请号：US184256

申请日：1988-04-21

申请人： Hideshi Miyatake ,  Masaki Kumanoya ,  Hideto Hidaka ,  Hiroyuki Yamasaki ,  Konishi Yasuhiro ,  Yuto Ikeda

发明人： Hideshi Miyatake ,  Masaki Kumanoya ,  Hideto Hidaka ,  Hiroyuki Yamasaki ,  Konishi Yasuhiro ,  Yuto Ikeda

IPC分类号： G11C11/409 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/417 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： G11C11/4076

摘要： A semiconductor dynamic RAM provided with an I/O load (5) rendered inactive during a writing cycle comprises a monostable multivibrator (16) for receiving a read/write indicating signal W for indicating reading and writing data from and into a memory cell (2) and outputting a signal W having a shorter duration than that of the signal W at a down edge of the signal W as a trigger. The output signal W of the monostable multivibrator (16) is supplied as a control signal for rendering the I/O load (5) inactive.

摘要翻译： 提供了在写周期期间变为不活动的I / O负载（5）的半导体动态RAM包括用于接收读/写指示信号和上行和下拉以指示从存储单元读取和写入数据的单稳态多谐振荡器（16） 2），并输出信号和上行和下拉沿W信号和上行和下拉沿W信号和上升沿和W的持续时间W作为触发。 单稳态多谐振荡器（16）的输出信号和上升沿W被提供为用于使I / O负载（5）无效的控制信号。

公开(公告)号：US08731263B2

公开(公告)日：2014-05-20

申请号：US12032266

申请日：2008-02-15

申请人： Hiroshi Fukatsu ,  Maki Minakuchi ,  Muneyasu Kazuno ,  Kenichi Niwa ,  Hiroyuki Yamasaki

发明人： Hiroshi Fukatsu ,  Maki Minakuchi ,  Muneyasu Kazuno ,  Kenichi Niwa ,  Hiroyuki Yamasaki

IPC分类号： G06K9/00

CPC分类号： G06F19/321 ,  G06F19/00

摘要： The present invention comprises: a data storage unit for storing series image data obtained by medical image acquisition equipment and object data containing image acquisition conditions for the series image data and the specific information for specifying other series image data related to the series image data; an information management unit for generating a thumbnail image that represents combination information of the presently obtained series image data and the past related series image data by referring to the object data; and a display unit for displaying the thumbnail image.

摘要翻译： 本发明包括：数据存储单元，用于存储由医学图像获取设备获得的系列图像数据和包含用于串行图像数据的图像获取条件的对象数据和用于指定与该系列图像数据相关的其他系列图像数据的特定信息; 信息管理单元，用于通过参照对象数据生成表示当前获得的串联图像数据和过去相关串联图像数据的组合信息的缩略图图像; 以及用于显示缩略图图像的显示单元。