公开(公告)号：US20110006403A1

公开(公告)日：2011-01-13

申请号：US12784162

申请日：2010-05-20

申请人： Katsuya OKUMURA ,  Hiroki WAKIMOTO ,  Kazuo SHIMOYAMA ,  Tomoyuki YAMAZAKI

发明人： Katsuya OKUMURA ,  Hiroki WAKIMOTO ,  Kazuo SHIMOYAMA ,  Tomoyuki YAMAZAKI

IPC分类号： H01L29/06 ,  H01L21/302

CPC分类号： H01L29/0661 ,  H01L21/76224 ,  H01L29/0619 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/66333 ,  H01L29/7395

摘要： A semiconductor device is disclosed which includes active section 100, edge termination section 110 having a voltage blocking structure and disposed around active section 100, and separation section 120 having a device separation structure and disposed around edge termination section 110. A surface device structure is formed on the first major surface of active section 100, trench 23 is formed in separation section 120 from the second major surface side, and p+-type separation region 24 is formed on the side wall of trench 23 such that p+-type separation region 24 is in contact with p-type channel stopper region 21 formed in the surface portion on the first major surface side and p-type collector layer 9 formed in the surface portion on the second major surface side. The semiconductor device and the method for manufacturing the semiconductor device according to the invention facilitate preventing the reverse blocking voltage from decreasing and shorten the manufacturing time of the semiconductor device.

摘要翻译： 公开了一种半导体器件，其包括有源部分100，具有电压阻挡结构并设置在有源部分100周围的边缘终端部分110以及具有设备分离结构并且设置在边缘终端部分110周围的分离部分120.形成表面器件结构 在有源部分100的第一主表面上，在分离部分120中形成沟槽23与第二主表面侧，并且在沟槽23的侧壁上形成p +型分离区域24，使得p +型分离区域24为 与形成在第一主表面侧的表面部分中的p型沟道停止区域21和形成在第二主表面侧的表面部分中的p型集电极层9接触。 根据本发明的半导体器件和制造半导体器件的方法有助于防止反向阻断电压降低并缩短半导体器件的制造时间。

公开(公告)号：US20090146714A1

公开(公告)日：2009-06-11

申请号：US12330110

申请日：2008-12-08

申请人： Akira NAKAMORI ,  Takahiro MORI ,  Tomoyuki YAMAZAKI

发明人： Akira NAKAMORI ,  Takahiro MORI ,  Tomoyuki YAMAZAKI

IPC分类号： H03K5/12

CPC分类号： H03K17/168 ,  H03K17/163 ,  H03K2217/0036

摘要： A driver circuit facilitates reducing noises and losses and improving the driving performances thereof without connecting a series circuit of capacitor and a resistor to the gate of IGBT. The driver circuit includes a slope setting circuit that sets the gate voltage waveform of IGBT; and an operational amplifier that includes a non-inverting input terminal, to which an output voltage V* from slope setting circuit is inputted, and an inverting input terminal, to which a divided voltage Vgsf divided by resistors is inputted; and the operational amplifier outputs an output voltage Vout, proportional to the difference between the output voltage V* and the divided voltage Vgsf, to the gate of IGBT.

摘要翻译： 驱动电路有助于降低噪声和损耗，并提高其驱动性能，而无需将电容器和电阻器的串联电路连接到IGBT的栅极。 驱动电路包括设置IGBT栅极电压波形的斜坡设定电路; 以及运算放大器，其包括输入来自斜坡设定电路的输出电压V *的非反相输入端子和输入了由电阻器分压的分压电压Vgsf的反相输入端子; 并且运算放大器将与输出电压V *和分压Vgsf之间的差成比例的输出电压Vout输出到IGBT的栅极。

公开(公告)号：US20110198272A1

公开(公告)日：2011-08-18

申请号：US13024701

申请日：2011-02-10

申请人： Tomoyuki YAMAZAKI

发明人： Tomoyuki YAMAZAKI

IPC分类号： B01D15/08

CPC分类号： G01N30/34 ,  B01D15/163 ,  B01D15/166 ,  B01D15/247 ,  G01N30/08 ,  G01N30/20 ,  G01N30/26 ,  G01N30/32 ,  G01N30/462 ,  G01N30/80 ,  G01N30/82 ,  G01N2030/085 ,  G01N2030/202 ,  G01N2030/8411 ,  G01N2030/8429 ,  G01N2030/8494

摘要： The present invention aims at providing a preparative separation/purification system for vaporizing an eluate in a short period of time, while enhancing the efficiency of collecting the target substance by accelerating the initiation of collecting the eluate. The preparative separation/purification system in which water containing a target component is passed through a column 8 to capture the target component in the column 8 and then a solvent is passed through it to collect the target compound, includes: a liquid supply means 7 for supplying a solvent to the column 8, with the target component captured in the column 8, while the column 8 is vertically held with the inlet end thereof directed downwards and the discharge end thereof directed upwards, the solvent having a low solubility to water and having a specific gravity greater than that of water; a passage selection means 12 for changing the passage configuration so that a solution exiting from the column 8 is selectively sent to either a collection passage 13 or a disposal passage 14; a passage control means 30 for controlling the passage selection means 12 so that, when water exits from the column 8, the water is sent to the disposal passage 14, and when solution containing solvent exits from the column 8, the solution is sent to the collection passage 13; and a flow rate control means 30 for controlling so that the water is supplied at a first flow rate to the disposal passage 14, and the solution containing solvent is supplied to the collection passage 13 at a flow rate lower than the first flow rate.

摘要翻译： 本发明旨在提供一种用于在短时间内蒸发洗脱液的制备分离/纯化系统，同时通过加速收集洗脱液的开始提高收集目标物质的效率。 将含有目标成分的水通过塔8捕获塔8中的目标成分，然后通过溶剂以收集目标化合物的制备型分离/纯化系统包括：液体供应装置7，用于 向柱8供应溶剂，其中目标组分捕获在塔8中，同时柱8垂直保持，其入口端向下指向其排出端向上，溶剂对水的溶解度低，并且具有 比重大于水; 用于改变通道构造的通道选择装置12，使得从塔8排出的溶液被选择性地送到收集通道13或处理通道14; 用于控制通道选择装置12的通道控制装置30，使得当水从塔8排出时，水被送到处理通道14，并且当含有溶剂的溶液从塔8排出时，溶液被送到 收集通道13; 以及流量控制装置30，用于控制水以第一流量供给到处理通道14，并且含有溶剂的溶液以低于第一流量的流量供给到收集通道13。

公开(公告)号：US20100019342A1

公开(公告)日：2010-01-28

申请号：US12507735

申请日：2009-07-22

申请人： Ryouichi KAWANO ,  Tomoyuki YAMAZAKI ,  Michio NEMOTO ,  Mituhiro KAKEFU

发明人： Ryouichi KAWANO ,  Tomoyuki YAMAZAKI ,  Michio NEMOTO ,  Mituhiro KAKEFU

IPC分类号： H01L29/861

CPC分类号： H01L29/8611 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/404 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor device having a pn-junction diode structure that includes anode diffusion region including edge area, anode electrode on anode diffusion region, and insulator film on edge area of anode diffusion region, the area of anode electrode above anode diffusion region with insulator film interposed between anode electrode and anode diffusion region is narrower than the area of insulator film on edge area of anode diffusion region.

摘要翻译： 在具有pn结二极管结构的半导体器件中，包括阳极扩散区域包括边缘区域，阳极扩散区域上的阳极电极和阳极扩散区域的边缘区域上的绝缘膜，阳极扩散区域上方的绝缘膜的阳极电极面积 介于阳极电极和阳极扩散区之间的绝缘膜的面积比阳极扩散区边缘区域的面积窄。

公开(公告)号：US20090302346A1

公开(公告)日：2009-12-10

申请号：US12479353

申请日：2009-06-05

申请人： Tomoyuki YAMAZAKI

发明人： Tomoyuki YAMAZAKI

IPC分类号： H01L29/739 ,  H01L29/78

CPC分类号： H01L29/7395 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813

摘要： A surface between gate electrodes in an MOS gate structure is patterned so that missing portions are partially provided in surfaces of n+ emitter regions to thereby enlarge surface areas of p+ contact regions surrounded by the surfaces of the n+ emitter regions. In this manner, a highly reliable MOS type semiconductor device is provided which is improved in breakdown tolerance by suppressing an increase in the gain of a parasitic transistor caused by photo pattern defects produced easily in accordance with minute patterning in a process design rule.

摘要翻译： 在MOS栅极结构中的栅电极之间的表面被图案化，使得在n +发射极区域的表面中部分地设置缺损部分，从而扩大由n +发射极区域的表面包围的p +接触区域的表面积。 以这种方式，提供了一种高度可靠的MOS型半导体器件，其通过抑制由于根据工艺设计规则中的微小图案化而容易地产生的光图案缺陷引起的寄生晶体管的增益增加，从而提高耐击穿能力。