公开(公告)号：US07245549B2

公开(公告)日：2007-07-17

申请号：US11058302

申请日：2005-02-16

申请人： Kazufumi Komura ,  Yoshiharu Kato ,  Satoru Kawamoto

发明人： Kazufumi Komura ,  Yoshiharu Kato ,  Satoru Kawamoto

IPC分类号： G11C8/00

CPC分类号： G11C11/4094 ,  G11C11/4076 ,  G11C2207/005

摘要： A semiconductor memory device is provided that can conduct the equalizing operation of bit lines with a low current consumption while maintaining a normal accessing speed and the chip area, and a control method thereof. In a semiconductor memory device of the shared sense amplification system, in a predetermined number of times which is (k−1) times or less among k-times of continuous word line selections of a selected memory block, the bit line separation gate of the unselected memory block is rendered conductive in the active period of the equalizing unit after the word line selection. Also, a circuit that equalizes a wiring higher in the capacity component is driven by a higher voltage level according to the wiring capacity component of the sense amplification power supply line and the bit lines.

摘要翻译： 提供一种半导体存储装置及其控制方法，其可以在保持正常访问速度和芯片面积的同时以低电流消耗进行位线的均衡操作。 在共享读出放大系统的半导体存储器件中，在所选择的存储器块的连续字线选择的k次之间的预定次数（k-1）倍以下的情况下，位线分离门 未选择的存储块在字线选择之后的均衡单元的有效周期内变为导通。 此外，根据感测放大电源线和位线的布线容量分量，通过更高的电压电平来驱动均衡电容分量较高的布线的电路。

公开(公告)号：US06956777B2

公开(公告)日：2005-10-18

申请号：US10299775

申请日：2002-11-20

申请人： Kazufumi Komura ,  Satoru Kawamoto

发明人： Kazufumi Komura ,  Satoru Kawamoto

IPC分类号： G11C11/403 ,  G11C11/401 ,  G11C11/406 ,  G11C29/00 ,  G11C29/04

CPC分类号： G11C29/783 ,  G11C11/406 ,  G11C2207/2227

摘要： There are intended to provide a semiconductor memory device capable of data access with higher speed and improvement of data transfer rate by shortening refresh operation cycle by stable low-current-consumption operation, and a control method of such a semiconductor memory device. In advance to the refresh operation mode signal M(I), control signal SW is outputted. Consequently, the switching sections select stored address bus Ladd from each storing section and stored-redundancy-judgment-result bus LJ and output address information subject to refresh operation to a word-line-driving-system circuit. After the address information from each storing section is outputted, a control signal LCH is outputted. As a result, an address switching section selects refresh address bys Add(I) subject to next refresh operation and each storing section stores address Add(I) fetched in an internal address bus IAdd and its redundancy judgment result RJ(I).

摘要翻译： 旨在通过稳定的低电流消耗操作来缩短刷新操作周期，以及这种半导体存储器件的控制方法，提供能够以更高速度进行数据访问并提高数据传输速率的半导体存储器件。 提前到刷新操作模式信号M（I），输出控制信号SW。 因此，切换部分从存储部分选择存储的地址总线Ladd和存储的冗余判断结果总线LJ以及进行刷新操作的输出地址信息到字线驱动系统电路。 在输出来自每个存储部分的地址信息之后，输出控制信号LCH。 结果，地址切换部分选择通过下一次刷新操作的添加（I）的刷新地址，并且每个存储部分存储在内部地址总线IAdd中获取的地址Add（I）及其冗余判断结果RJ（I）。

公开(公告)号：US06795328B2

公开(公告)日：2004-09-21

申请号：US10355079

申请日：2003-01-31

申请人： Yoshiharu Kato ,  Kazufumi Komura ,  Satoru Kawamoto

发明人： Yoshiharu Kato ,  Kazufumi Komura ,  Satoru Kawamoto

IPC分类号： G11C506

CPC分类号： G11C7/065 ,  G11C7/18 ,  G11C8/08 ,  G11C2207/065 ,  H01L27/10897

摘要： A semiconductor memory device having a driver transistor for the supply of electric power is provided, which can diminish leakage current during inactivation while ensuring sufficient power supply capability for a sense amplifier during activation. Gate width is provided at every two bit line pair pitches perpendicularly to a bit line direction, and a supply voltage VDD and a reference voltage VSS are fed to PMOS transistors SP0, SP0_ to SP3, sP3_ and NMOS transistors SN0, SN0_ to SN3, SN3_. In driver-dedicated PMOS transistors P1, P2, and NMOS transistors N1, N2, gate width is adjusted using the length of two bit line pair pitches as a maximum value, while gate length is adjusted using an adjusting region &Dgr;L, whereby there can be obtained driver-dedicated MOS transistors P1, P2, N1, and N2 in an appropriately adjusted state with respect to such characteristics contrary to each other as ensuring sufficient current supply capability and diminishing a tailing current.

摘要翻译： 提供了具有用于供电的驱动晶体管的半导体存储器件，其可以在激活期间确保足够的读出放大器的电源能力的同时减少失电期间的漏电流。 栅极宽度设置在垂直于位线方向的每两个位线对间距处，并且电源电压VDD和参考电压VSS被馈送到PMOS晶体管SP0，SP0_至SP3，sP3_和NMOS晶体管SN0，SN0_至SN3，SN3_ 。 在驱动器专用PMOS晶体管P1，P2和NMOS晶体管N1，N2中，使用两个位线对间距的长度作为最大值来调整栅极宽度，而使用调整区域DeltaL来调整栅极长度，由此可以 获得的驱动器专用MOS晶体管P1，P2，N1和N2在适当调整的状态下相对于彼此相反，因为确保足够的电流供应能力和减小尾流电流。

公开(公告)号：US07495990B2

公开(公告)日：2009-02-24

申请号：US11806721

申请日：2007-06-04

申请人： Kazufumi Komura ,  Yoshiharu Kato ,  Satoru Kawamoto

发明人： Kazufumi Komura ,  Yoshiharu Kato ,  Satoru Kawamoto

IPC分类号： G11C8/00

CPC分类号： G11C11/4094 ,  G11C11/4076 ,  G11C2207/005

摘要： It is an object to provide a semiconductor memory device that can conduct the equalizing operation of bit lines with a low current consumption while maintaining a normal accessing speed and the chip area, and a control method thereof. In a semiconductor memory device of the shared sense amplification system, in a predetermined number of times which is (k−1) times or less among k-times of continuous word line selections of a selected memory block, the bit line separation gate of the unselected memory block is rendered conductive in the active period of the equalizing unit after the word line selection. Also, a circuit that equalizes a wiring higher in the capacity component is driven by a higher voltage level according to the wiring capacity component of the sense amplification power supply line and the bit lines, to thereby equalize the power supply line and the bit line in the equal time, thereby being capable of preventing the short-circuiting within the sense amplifier.

摘要翻译： 本发明的目的是提供一种半导体存储器件及其控制方法，该半导体存储器件可以在保持正常访问速度和芯片面积的同时以低电流消耗进行位线的均衡操作。 在共享读出放大系统的半导体存储器件中，在所选择的存储器块的连续字线选择的k次之间的预定次数（k-1）倍以下的情况下，位线分离门 未选择的存储块在字线选择之后的均衡单元的有效周期内变为导通。 此外，根据感测放大电源线和位线的布线电容分量，通过较高的电压电平驱动均衡电容分量较高的布线的电路，从而使电源线和位线的均匀化 相等的时间，从而能够防止读出放大器内的短路。

公开(公告)号：US20050157574A1

公开(公告)日：2005-07-21

申请号：US11058302

申请日：2005-02-16

申请人： Kazufumi Komura ,  Yoshiharu Kato ,  Satoru Kawamoto

发明人： Kazufumi Komura ,  Yoshiharu Kato ,  Satoru Kawamoto

IPC分类号： G11C7/00 ,  G11C11/4076 ,  G11C11/4094

CPC分类号： G11C11/4094 ,  G11C11/4076 ,  G11C2207/005

摘要： It is an object to provide a semiconductor memory device that can conduct the equalizing operation of bit lines with a low current consumption while maintaining a normal accessing speed and the chip area, and a control method thereof. In a semiconductor memory device of the shared sense amplification system, in a predetermined number of times which is (k−1) times or less among k-times of continuous word line selections of a selected memory block, the bit line separation gate of the unselected memory block is rendered conductive in the active period of the equalizing unit after the word line selection. Also, a circuit that equalizes a wiring higher in the capacity component is driven by a higher voltage level according to the wiring capacity component of the sense amplification power supply line and the bit lines, to thereby equalize the power supply line and the bit line in the equal time, thereby being capable of preventing the short-circuiting within the sense amplifier.

摘要翻译： 本发明的目的是提供一种半导体存储器件及其控制方法，该半导体存储器件可以在保持正常访问速度和芯片面积的同时以低电流消耗进行位线的均衡操作。 在共享读出放大系统的半导体存储器件中，在所选择的存储器块的连续字线选择的k次之间的预定次数（k-1）倍以下的情况下，位线分离门 未选择的存储块在字线选择之后的均衡单元的有效周期内变为导通。 此外，根据感测放大电源线和位线的布线电容分量，通过较高的电压电平驱动均衡电容分量较高的布线的电路，从而使电源线和位线的均匀化 相等的时间，从而能够防止读出放大器内的短路。

公开(公告)号：US06879200B2

公开(公告)日：2005-04-12

申请号：US09921561

申请日：2001-08-06

申请人： Kazufumi Komura ,  Satoru Kawamoto

发明人： Kazufumi Komura ,  Satoru Kawamoto

IPC分类号： G11C8/00 ,  G11C11/4076 ,  H03K5/00 ,  H03K5/14 ,  H03H11/26

CPC分类号： H03K5/133 ,  H03K2005/00065

摘要： A delay circuit including a delay section having two or more predetermined delay stages is disclosed. Each predetermined delay stage adds a predetermined delay time to an input signal. The delay circuit also includes selecting switch sections. At least one of the selecting switch sections includes: a buffer section for receiving a delayed input signal from one of the delay stages and a selecting section means directly connected to the buffer section for activating the buffer section to establish a delay path, wherein an output signal from the delay path has a desired delay time.

摘要翻译： 公开了一种包括具有两个或多个预定延迟级的延迟部分的延迟电路。 每个预定延迟级向输入信号添加预定的延迟时间。 延迟电路还包括选择开关部分。 所述选择开关部分中的至少一个包括：用于从所述延迟级之一接收延迟的输入信号的缓冲器部分和直接连接到所述缓冲器部分的用于激活所述缓冲器部分以建立延迟路径的选择部分装置，其中输出 来自延迟路径的信号具有期望的延迟时间。

公开(公告)号：US20070237014A1

公开(公告)日：2007-10-11

申请号：US11806721

申请日：2007-06-04

申请人： Kazufumi Komura ,  Yoshiharu Kato ,  Satoru Kawamoto

发明人： Kazufumi Komura ,  Yoshiharu Kato ,  Satoru Kawamoto

IPC分类号： G11C7/00

CPC分类号： G11C11/4094 ,  G11C11/4076 ,  G11C2207/005

摘要： It is an object to provide a semiconductor memory device that can conduct the equalizing operation of bit lines with a low current consumption while maintaining a normal accessing speed and the chip area, and a control method thereof. In a semiconductor memory device of the shared sense amplification system, in a predetermined number of times which is (k−1) times or less among k-times of continuous word line selections of a selected memory block, the bit line separation gate of the unselected memory block is rendered conductive in the active period of the equalizing unit after the word line selection. Also, a circuit that equalizes a wiring higher in the capacity component is driven by a higher voltage level according to the wiring capacity component of the sense amplification power supply line and the bit lines, to thereby equalize the power supply line and the bit line in the equal time, thereby being capable of preventing the short-circuiting within the sense amplifier.

摘要翻译： 本发明的目的是提供一种半导体存储器件及其控制方法，该半导体存储器件可以在保持正常访问速度和芯片面积的同时以低电流消耗进行位线的均衡操作。 在共享读出放大系统的半导体存储器件中，在所选择的存储器块的连续字线选择的k次之间的预定次数（k-1）倍以下的情况下，位线分离门 未选择的存储块在字线选择之后的均衡单元的有效周期内变为导通。 此外，根据感测放大电源线和位线的布线电容分量，通过较高的电压电平驱动均衡电容分量较高的布线的电路，从而使电源线和位线的均匀化 相等的时间，从而能够防止读出放大器内的短路。

公开(公告)号：US06490215B2

公开(公告)日：2002-12-03

申请号：US09861545

申请日：2001-05-22

申请人： Kazufumi Komura ,  Takaaki Furuyama ,  Satoru Kawamoto

发明人： Kazufumi Komura ,  Takaaki Furuyama ,  Satoru Kawamoto

IPC分类号： G11C700

CPC分类号： G11C11/406

摘要： A semiconductor memory device that suppresses an increase in the circuit area which is originated from the layout of address signal lines. The semiconductor memory device includes refresh address counters, a switch circuit, and address holding circuits. The refresh address counters generate refresh address signals associated with banks in response to a refresh request signal. The switch circuit selectively outputs the external address signal and a refresh address signal generated by one of the refresh address counters in accordance with the refresh request signal. Each of the address holding circuits holds the refresh address signal or the external address signal output from the switch circuit and supplies the held address signal to an associated one of the banks.

摘要翻译： 一种半导体存储器件，其抑制来自地址信号线的布局的电路面积的增加。 半导体存储器件包括刷新地址计数器，开关电路和地址保持电路。 刷新地址计数器响应于刷新请求信号产生与存储体相关联的刷新地址信号。 开关电路根据刷新请求信号有选择地输出外部地址信号和由刷新地址计数器之一产生的刷新地址信号。 每个地址保持电路保持从开关电路输出的刷新地址信号或外部地址信号，并将保持的地址信号提供给相关的一个存储体。

公开(公告)号：US07514781B2

公开(公告)日：2009-04-07

申请号：US11602230

申请日：2006-11-21

申请人： Satoru Kawamoto

发明人： Satoru Kawamoto

IPC分类号： H01L23/14

CPC分类号： H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K1/0366 ,  H05K3/4688 ,  H05K2201/0191 ,  H05K2201/029 ,  Y10T428/24917 ,  H01L2924/00

摘要： A circuit substrate includes a plurality of dielectric members and a plurality of wiring patterns. The plurality of wiring patterns are stacked on one another through the plurality of dielectric members. The plurality of dielectric members includes a mount dielectric member. A first wiring pattern of the plurality of wiring patterns is provided on a side of the mount dielectric member. A second wiring pattern of the plurality of wiring patterns is provided on an opposite side of the mount dielectric member. A first length is a length between a reinforcing medium of the mount dielectric member and the opposite side of the mount dielectric member in a thickness direction. A second length is a length between the reinforcing medium of the mount dielectric member and the side of the mount dielectric member in the thickness direction. The first length is smaller than the second length.

摘要翻译： 电路基板包括多个电介质构件和多个布线图案。 多个布线图案通过多个电介质构件彼此堆叠。 多个电介质构件包括安装电介质构件。 多个布线图案的第一布线图案设置在安装电介质构件的一侧。 多个布线图案的第二布线图案设置在安装电介质构件的相对侧上。 第一长度是在安装电介质构件的加强介质和安装电介质构件的厚度方向的相对侧之间的长度。 第二长度是在安装电介质构件的加强介质和安装电介质构件的厚度方向的一侧之间的长度。 第一长度小于第二长度。

公开(公告)号：US07358778B2

公开(公告)日：2008-04-15

申请号：US11482129

申请日：2006-07-07

申请人： Kenta Kato ,  Satoru Kawamoto

发明人： Kenta Kato ,  Satoru Kawamoto

IPC分类号： H03K5/22 ,  H03K5/153

CPC分类号： H03K5/08 ,  G01R19/16519 ,  G11C5/143 ,  G11C16/30

摘要： A voltage detection circuit for accurately detecting a voltage while suppressing the voltage fluctuation due to the off-leak current of a transistor. The voltage detection circuit includes first and second capacitors, first and second transistors, a comparator, and a control circuit. The capacitors are connected in series to generate a division voltage corresponding to a high voltage by the capacitors. The potential at a node between the first capacitor and the second capacitor is reset to ground potential when the transistors are activated. When the potential at the node reaches a predetermined potential, the first transistor is inactivated, and then the second transistor is inactivated.

摘要翻译： 一种电压检测电路，用于在抑制由晶体管的漏电流引起的电压波动的同时精确地检测电压。 电压检测电路包括第一和第二电容器，第一和第二晶体管，比较器和控制电路。 电容器串联连接以产生对应于电容器的高电压的分压。 当晶体管被激活时，第一电容器和第二电容器之间的节点处的电位被复位为接地电位。 当节点处的电位达到预定电位时，第一晶体管失活，然后第二晶体管失活。