公开(公告)号：US07601485B2

公开(公告)日：2009-10-13

申请号：US11360809

申请日：2006-02-24

申请人： Kazuma Sekiya ,  Takashi Ono ,  Akihito Kawai

发明人： Kazuma Sekiya ,  Takashi Ono ,  Akihito Kawai

IPC分类号： G03F7/26 ,  G03F9/00

CPC分类号： G03F7/2022 ,  G03F1/00 ,  G03F7/70425 ,  G03F7/70466

摘要： An exposure method for exposing a resist film disposed on one surface of a wafer includes a first exposure step of locating an exposure mask at a first predetermined position with respect to the wafer, and exposing the resist film. The exposure method further includes a second exposure step of displacing the exposure mask relative to the wafer by a predetermined dimension in a predetermined direction to locate the exposure mask at a second predetermined position, and exposing the resist film.

摘要翻译： 用于曝光设置在晶片的一个表面上的抗蚀剂膜的曝光方法包括：将曝光掩模相对于晶片定位在第一预定位置并使抗蚀剂膜曝光的第一曝光步骤。 曝光方法还包括第二曝光步骤，使曝光掩模相对于晶片沿预定方向移动预定尺寸，以将曝光掩模定位在第二预定位置，并使抗蚀剂膜曝光。

公开(公告)号：US20060199114A1

公开(公告)日：2006-09-07

申请号：US11360809

申请日：2006-02-24

申请人： Kazuma Sekiya ,  Takashi Ono ,  Akihito Kawai

发明人： Kazuma Sekiya ,  Takashi Ono ,  Akihito Kawai

IPC分类号： G03C5/00

CPC分类号： G03F7/2022 ,  G03F1/00 ,  G03F7/70425 ,  G03F7/70466

摘要： An exposure method for exposing a resist film disposed on one surface of a wafer includes a first exposure step of locating an exposure mask at a first predetermined position with respect to the wafer, and exposing the resist film. The exposure method further includes a second exposure step of displacing the exposure mask relative to the wafer by a predetermined dimension in a predetermined direction to locate the exposure mask at a second predetermined position, and exposing the resist film.

公开(公告)号：US20080076256A1

公开(公告)日：2008-03-27

申请号：US11902046

申请日：2007-09-18

申请人： Akihito Kawai ,  Takashi Ono ,  Hiroshi Morikazu

发明人： Akihito Kawai ,  Takashi Ono ,  Hiroshi Morikazu

IPC分类号： H01L21/311

CPC分类号： H01L21/3065 ,  B23K26/389 ,  B24B7/228 ,  H01L21/02057 ,  H01L21/76898

摘要： A method of forming a via hole reaching a bonding pad in a wafer, which have a plurality of devices on the front surface of a substrate and bonding pads on each of the devices, by applying a pulse laser beam from the rear surface of the substrate, comprising the steps of:affixing a protective member to the front surface of the substrate;grinding the rear surface of the substrate having the protective member affixed to the front surface to reduce the thickness of the wafer to a predetermined value;forming via holes in the substrate by applying a pulse laser beam from the rear surface of the substrate of the wafer having the predetermined thickness; andetching the wafer having the via holes in the substrate from the rear surface of the substrate.

摘要翻译： 一种通过从衬底的后表面施加脉冲激光束，形成通孔到达衬底的接合焊盘的方法，该通孔在衬底的前表面上具有多个器件和每个器件上的接合焊盘 包括以下步骤：将保护构件固定在基板的前表面上; 研磨具有固定在前表面的保护构件的基板的后表面，以将晶片的厚度减小到预定值; 通过从具有预定厚度的晶片的衬底的后表面施加脉冲激光束，在衬底中形成通孔; 并且从衬底的后表面蚀刻在衬底中具有通孔的晶片。

公开(公告)号：US20060073705A1

公开(公告)日：2006-04-06

申请号：US11237690

申请日：2005-09-29

申请人： Kazuhisa Arai ,  Shinichi Fujisawa ,  Ryo Matsuhashi ,  Takashi Ono ,  Toshihiro Funanaka ,  Jun Hachiya ,  Akihito Kawai

发明人： Kazuhisa Arai ,  Shinichi Fujisawa ,  Ryo Matsuhashi ,  Takashi Ono ,  Toshihiro Funanaka ,  Jun Hachiya ,  Akihito Kawai

IPC分类号： H01L21/461

CPC分类号： H01L21/78 ,  H01L21/3065

摘要： A method for dividing a semiconductor wafer along a plurality of streets, the semiconductor wafer having a face on which a plurality of rectangular regions are defined by the streets arranged in a lattice pattern, and a semiconductor device is formed in each of the rectangular regions. This method comprises a protective member coating step of coating the face of the semiconductor wafer with a protective member, a resist film coating step of coating the back of the semiconductor wafer, except sites corresponding to the streets, with a resist film, and a plasma etching step of applying plasma etching to the back of the semiconductor wafer to divide the semiconductor wafer along the streets.

摘要翻译： 一种用于沿着多个街道划分半导体晶片的方法，所述半导体晶片具有由以格子状布置的街道限定多个矩形区域的面，并且在每个矩形区域中形成半导体器件。 该方法包括用保护部件涂覆半导体晶片的表面的保护部件涂布工序，除了与街道对应的位置以外的半导体晶片的背面，用抗蚀剂膜和等离子体 将等离子体蚀刻施加到半导体晶片的背面以沿着街道划分半导体晶片的蚀刻步骤。

公开(公告)号：US20060088983A1

公开(公告)日：2006-04-27

申请号：US11251933

申请日：2005-10-18

申请人： Shinichi Fujisawa ,  Ryou Matsuhashi ,  Takashi Ono ,  Toshihiro Funanaka ,  Jun Hachiya ,  Akihito Kawai

发明人： Shinichi Fujisawa ,  Ryou Matsuhashi ,  Takashi Ono ,  Toshihiro Funanaka ,  Jun Hachiya ,  Akihito Kawai

IPC分类号： H01L21/78 ,  H01L21/302

CPC分类号： H01L21/67132 ,  H01L21/304 ,  H01L21/3065 ,  H01L21/31138 ,  H01L21/67092 ,  H01L21/78

摘要： In order to efficiently divide the wafer into individual devices in dicing the wafer without deteriorating the quality of the devices, the front surface of the wafer is coated with a resist film except the regions corresponding to the streets, grooves of a depth corresponding to the finished thickness of the devices are formed by plasma etching in the regions corresponding to the streets, and the back surface of the wafer is ground so that the grooves are exposed from the side of the back surface and that the wafer is divided into individual devices.

摘要翻译： 为了在不影响器件质量的情况下将晶片有效地划分成各个器件，晶片的前表面涂覆有抗蚀剂膜，除了对应于街道的区域，对应于完成的深度的槽 通过在与街道相对应的区域中的等离子体蚀刻形成器件的厚度，并且研磨晶片的背面，使得凹槽从背面的侧面露出，并且将晶片分成单独的器件。

公开(公告)号：US08389386B2

公开(公告)日：2013-03-05

申请号：US13088591

申请日：2011-04-18

申请人： Akihito Kawai ,  Koichi Kondo

发明人： Akihito Kawai ,  Koichi Kondo

IPC分类号： H01L21/00

CPC分类号： H01L21/304 ,  B24B1/00 ,  B24B7/228 ,  H01L21/67092 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L24/16 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/16145 ,  H01L2224/73204 ,  H01L2224/75744 ,  H01L2224/75988 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01061 ,  H01L2224/81

摘要： A manufacturing method for a stacked wafer configured by bonding a mother wafer having a plurality of first semiconductor device and a stacking wafer having a plurality of second semiconductor devices. The manufacturing method includes the steps of attaching a protective member to the front side of the stacking wafer to protect the second semiconductor devices, next grinding the back side of the stacking wafer, next bonding the front side of a reinforcing wafer through a bonding layer to the back side of the stacking wafer, next dividing the stacking wafer together with the reinforcing wafer into the plural second semiconductor devices, next bonding the front side of each second semiconductor device to the front side of the mother wafer to thereby connect the electrodes of each second semiconductor device to the electrodes of the corresponding first semiconductor device of the mother wafer, and finally grinding the reinforcing wafer bonded to the back side of each second semiconductor device to thereby remove the reinforcing wafer.

摘要翻译： 一种堆叠晶片的制造方法，其通过将具有多个第一半导体器件的母晶片和具有多个第二半导体器件的堆叠晶片接合而构成。 该制造方法包括以下步骤：将保护构件附接到堆叠晶片的前侧以保护第二半导体器件，接下来研磨堆叠晶片的背面，接下来通过粘合层将加强晶片的前侧粘合到 堆叠晶片的背面，接下来将堆叠晶片与增强晶片一起分割成多个第二半导体器件，接下来将每个第二半导体器件的前侧接合到母晶片的前侧，从而将每个 将第二半导体器件施加到母晶片的相应的第一半导体器件的电极，并且最后研磨结合到每个第二半导体器件的背面的加强晶片，从而去除加强晶片。

公开(公告)号：US20090181519A1

公开(公告)日：2009-07-16

申请号：US12345222

申请日：2008-12-29

申请人： Kazuhisa Arai ,  Akihito Kawai

发明人： Kazuhisa Arai ,  Akihito Kawai

IPC分类号： H01L21/30

CPC分类号： H01L21/78 ,  B23K26/032 ,  B23K26/044 ,  B23K26/0853 ,  B23K26/382 ,  B23K26/40 ,  B23K2103/50 ,  H01L21/6836 ,  H01L24/33 ,  H01L24/94 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/14

摘要： A lamination device manufacturing method for manufacturing a lamination device using a reinforced wafer formed with an annular reinforced portion, includes a wafer lamination step in which a rear surface of the reinforced wafer corresponding to the device area is faced to and joined to the front surface of an underlying wafer with corresponding streets aligned with each other, thus forming a lamination wafer; an electrode connection step in which a via-hole is formed at a position where an electrode is formed in each of the devices of the reinforced wafer constituting part of the lamination wafer, so as to reach a corresponding electrode formed in each of the devices of the underlying wafer, and the via-hole is filled with a conductive material to connect the electrodes; and a division step in which after the electrode connection step is executed, the lamination wafer is cut along the streets and divided into individual lamination devices.

摘要翻译： 一种用于制造使用形成有环形增强部分的增强晶片的层压装置的层压装置制造方法，包括晶片层压步骤，其中与装置区域相对应的加强晶片的后表面面向并连接到 具有对应的街道的底层晶片彼此对准，从而形成层压晶片; 电极连接步骤，其中在构成部分叠层晶片的增强晶片的每个器件中形成电极的位置处形成通孔，以便到达形成在每个器件中的相应电极 底部晶片和通孔填充有导电材料以连接电极; 以及划分步骤，其中在执行电极连接步骤之后，沿着街道切割层压晶片，并将其分割成单独的层压装置。

公开(公告)号：US20060012056A1

公开(公告)日：2006-01-19

申请号：US11178278

申请日：2005-07-12

申请人： Shinji Ueno ,  Akihito Kawai

发明人： Shinji Ueno ,  Akihito Kawai

IPC分类号： H01L23/28

CPC分类号： H01L21/561 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3121 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor chip resin encapsulation method, including a resin filling and curing step of encapsulating a plurality of semiconductor chips, which have been bonded onto a substrate, in a molten resin, and curing the molten resin. The semiconductor chip resin encapsulation method further includes a grinding step of grinding an upper surface of the cured resin to decrease the thickness of the encapsulating resin to a predetermined value.

摘要翻译： 一种半导体芯片树脂封装方法，包括将已经结合到基板上的多个半导体芯片封装在熔融树脂中并使熔融树脂固化的树脂填充和固化步骤。 半导体芯片树脂封装方法还包括研磨固化树脂的上表面以将封装树脂的厚度减小到预定值的研磨步骤。

公开(公告)号：US20110256667A1

公开(公告)日：2011-10-20

申请号：US13088591

申请日：2011-04-18

申请人： Akihito Kawai ,  Koichi Kondo

发明人： Akihito Kawai ,  Koichi Kondo

IPC分类号： H01L21/78

CPC分类号： H01L21/304 ,  B24B1/00 ,  B24B7/228 ,  H01L21/67092 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L24/16 ,  H01L24/73 ,  H01L24/75 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/16145 ,  H01L2224/73204 ,  H01L2224/75744 ,  H01L2224/75988 ,  H01L2224/81005 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01061 ,  H01L2224/81

摘要： A manufacturing method for a stacked wafer configured by bonding a mother wafer having a plurality of first semiconductor device and a stacking wafer having a plurality of second semiconductor devices. The manufacturing method includes the steps of attaching a protective member to the front side of the stacking wafer to protect the second semiconductor devices, next grinding the back side of the stacking wafer, next bonding the front side of a reinforcing wafer through a bonding layer to the back side of the stacking wafer, next dividing the stacking wafer together with the reinforcing wafer into the plural second semiconductor devices, next bonding the front side of each second semiconductor device to the front side of the mother wafer to thereby connect the electrodes of each second semiconductor device to the electrodes of the corresponding first semiconductor device of the mother wafer, and finally grinding the reinforcing wafer bonded to the back side of each second semiconductor device to thereby remove the reinforcing wafer.

摘要翻译： 一种堆叠晶片的制造方法，其通过将具有多个第一半导体器件的母晶片和具有多个第二半导体器件的堆叠晶片接合而构成。 该制造方法包括以下步骤：将保护构件附接到堆叠晶片的前侧以保护第二半导体器件，接下来研磨堆叠晶片的背面，接下来通过粘合层将加强晶片的前侧粘合到 堆叠晶片的背面，接下来将堆叠晶片与增强晶片一起分割成多个第二半导体器件，接下来将每个第二半导体器件的前侧接合到母晶片的前侧，从而将每个 将第二半导体器件施加到母晶片的相应的第一半导体器件的电极，并且最后研磨结合到每个第二半导体器件的背面的加强晶片，从而去除加强晶片。

公开(公告)号：US20110256665A1

公开(公告)日：2011-10-20

申请号：US13077125

申请日：2011-03-31

申请人： Akihito Kawai ,  Koichi Kondo

发明人： Akihito Kawai ,  Koichi Kondo

IPC分类号： H01L21/50 ,  H01L21/762

CPC分类号： H01L21/67092 ,  B24B1/00 ,  B24B7/228 ,  H01L21/187 ,  H01L21/304 ,  H01L21/6836 ,  H01L21/78 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/6834 ,  H01L2224/0348 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/13025 ,  H01L2224/16146 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01061 ,  H01L2924/014 ,  H01L2224/81

摘要： A manufacturing method for a stacked wafer composed of a mother wafer and a stacking wafer bonded together. The mother wafer has a plurality of first semiconductor devices and the stacking wafer has a plurality of second semiconductor devices respectively corresponding to the first semiconductor devices. The manufacturing method includes the steps of bonding the front side of a substrate through a bonding layer to the front side of the stacking wafer, next grinding the back side of the stacking wafer to reduce the thickness of the stacking wafer to a predetermined thickness, next stacking the unit of the stacking wafer and the substrate bonded together on the mother wafer in the condition where the back side of the stacking wafer is opposed to the front side of the mother wafer, thereby bonding electrodes exposed to the back side of each second semiconductor device to electrodes of each first semiconductor device formed on the front side of the mother wafer, and finally grinding the substrate bonded to the front side of the stacking wafer to thereby remove the substrate.

摘要翻译： 一种由母晶片和堆叠晶片组成的堆叠晶片的制造方法，其结合在一起。 母晶片具有多个第一半导体器件，并且堆叠晶片具有分别对应于第一半导体器件的多个第二半导体器件。 该制造方法包括以下步骤：通过结合层将基板的正面粘合到堆叠晶片的前侧，接下来研磨堆叠晶片的背面以将堆叠晶片的厚度减小到预定厚度，接下来 在堆叠晶片的背面与母晶片的前侧相对的状态下，将堆叠晶片和与基板结合在一起的单元堆叠在母晶片上，从而接合暴露于每个第二半导体的背面的电极 装置到形成在母晶片的前侧上的每个第一半导体器件的电极，并且最后研磨结合到堆叠晶片的前侧的衬底，从而去除衬底。