公开(公告)号：US08295080B2

公开(公告)日：2012-10-23

申请号：US12794077

申请日：2010-06-04

申请人： Kazuo Aizawa ,  Isamu Asano ,  Junji Tominaga ,  Alexander Kolobov ,  Paul Fons ,  Robert Simpson

发明人： Kazuo Aizawa ,  Isamu Asano ,  Junji Tominaga ,  Alexander Kolobov ,  Paul Fons ,  Robert Simpson

IPC分类号： G11C11/00

CPC分类号： H01L27/2409 ,  H01L27/2454 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1675 ,  H01L45/1683

摘要： A solid-state memory device includes: a superlattice laminate having plural crystal layers laminated therein, the crystal layers including first and second crystal layers having mutually opposite compositions; a lower electrode provided on a first surface in a laminating direction of the superlattice laminate; and an upper electrode provided on a second surface of the superlattice laminate in the laminating direction. The first crystal layer included in the superlattice laminate is made of a phase change compound. According to the present invention, the superlattice laminate laminated in opposite directions of the upper and lower electrodes is sandwiched between these electrodes. Therefore, when an electric energy is applied to the superlattice laminate via these electrodes, a uniform electric energy can be applied to a laminated surface of the superlattice laminate. Accordingly, fluctuation of a resistance is small even when information is repeatedly rewritten, and data can be read stably as a result.

摘要翻译： 固体存储器件包括：层叠有多个晶体层的超晶格层压体，所述晶体层包括具有相互相反组成的第一和第二晶体层; 设置在所述超晶格层叠体的层叠方向的第一面上的下电极; 以及在层叠方向上设置在超晶格层压体的第二表面上的上电极。 包含在超晶格层叠体中的第一晶体层由相变化合物制成。 根据本发明，层叠在上下电极的相反方向上的超晶格层压体夹在这些电极之间。 因此，当通过这些电极向超晶格层叠体施加电能时，能够将均匀的电能施加到超晶格层叠体的层叠表面。 因此，即使重复地重写信息，电阻的波动也小，结果可以稳定地读出数据。

公开(公告)号：US20100284218A1

公开(公告)日：2010-11-11

申请号：US12772340

申请日：2010-05-03

申请人： Kazuo AIZAWA ,  Isamu Asano ,  Junji Tominaga ,  Alexander Kolobov ,  Paul Fons ,  Robert Simpson

发明人： Kazuo AIZAWA ,  Isamu Asano ,  Junji Tominaga ,  Alexander Kolobov ,  Paul Fons ,  Robert Simpson

IPC分类号： G11C11/34 ,  H01L29/66 ,  H01L21/06 ,  G11C29/00

CPC分类号： G11C13/0004 ,  G11C2213/55 ,  G11C2213/72 ,  G11C2213/79 ,  H01L45/065 ,  H01L45/144 ,  H01L45/1625

摘要： To include a superlattice laminate having laminated thereon a first crystal layer of which crystal lattice is a cubic crystal and in which positions of constituent atoms are reversibly replaced by application of energy, and a second crystal layer having a composition different from that of the first crystal layer, and an orientation layer that is an underlaying layer of the superlattice laminate and causes a laminated surface of the first crystal layer to be (111)-orientated. According to the present invention, the laminated surface of the first crystal layer can be (111)-orientated by using the orientation layer as an underlaying layer. In the first crystal layer of which laminated surface is (111)-orientated, a crystal structure reversibly changes when a relatively low energy is applied. Therefore, characteristics of a superlattice device having this crystal layer can be enhanced.

摘要翻译： 为了包括其上层压有晶格为立方晶的第一晶体层，其中构成原子的位置被能量可逆地替代的超晶格层压体，以及具有与第一晶体不同的组成的第二晶体层 层，以及作为超晶格层叠体的垫层的取向层，使第一结晶层的层叠表面（111）取向。 根据本发明，通过使用取向层作为底层，第一晶体层的层叠表面可以是（111）取向的。 在层叠表面为（111）取向的第一晶体层中，当施加相对低的能量时，晶体结构可逆地变化。 因此，可以提高具有该晶体层的超晶格器件的特性。

公开(公告)号：US08335106B2

公开(公告)日：2012-12-18

申请号：US12772340

申请日：2010-05-03

申请人： Kazuo Aizawa ,  Isamu Asano ,  Junji Tominaga ,  Alexander Kolobov ,  Paul Fons ,  Robert Simpson

发明人： Kazuo Aizawa ,  Isamu Asano ,  Junji Tominaga ,  Alexander Kolobov ,  Paul Fons ,  Robert Simpson

IPC分类号： G11C11/34

CPC分类号： G11C13/0004 ,  G11C2213/55 ,  G11C2213/72 ,  G11C2213/79 ,  H01L45/065 ,  H01L45/144 ,  H01L45/1625

摘要： To include a superlattice laminate having laminated thereon a first crystal layer of which crystal lattice is a cubic crystal and in which positions of constituent atoms are reversibly replaced by application of energy, and a second crystal layer having a composition different from that of the first crystal layer, and an orientation layer that is an underlaying layer of the superlattice laminate and causes a laminated surface of the first crystal layer to be (111)-orientated. According to the present invention, the laminated surface of the first crystal layer can be (111)-orientated by using the orientation layer as an underlaying layer. In the first crystal layer of which laminated surface is (111)-orientated, a crystal structure reversibly changes when a relatively low energy is applied. Therefore, characteristics of a superlattice device having this crystal layer can be enhanced.

摘要翻译： 为了包括其上层压有晶格为立方晶的第一晶体层，其中构成原子的位置被能量可逆地替代的超晶格层压体，以及具有与第一晶体不同的组成的第二晶体层 层，以及作为超晶格层叠体的垫层的取向层，使第一结晶层的层叠表面（111）取向。 根据本发明，通过使用取向层作为底层，第一晶体层的层叠表面可以是（111）取向的。 在层叠表面为（111）取向的第一晶体层中，当施加相对低的能量时，晶体结构可逆地变化。 因此，可以提高具有该晶体层的超晶格器件的特性。

公开(公告)号：US07692272B2

公开(公告)日：2010-04-06

申请号：US11334504

申请日：2006-01-19

申请人： Isamu Asano ,  Natsuki Sato ,  Wolodymyr Czubatyj ,  Jeffrey P. Fournier

发明人： Isamu Asano ,  Natsuki Sato ,  Wolodymyr Czubatyj ,  Jeffrey P. Fournier

IPC分类号： H01L31/0264

CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1625

摘要： A non-volatile memory element comprises a bottom electrode 12; a top electrode 15; and a recording layer 13 containing phase change material and a block layer 14 that can block phase change of the recording layer 13, provided between the bottom electrode 12 and the top electrode 15. The block layer 14 is constituted of material having an electrical resistance that is higher than that of material constituting the recording layer 13. The block layer 14 suppresses the radiation of heat towards the top electrode 15 and greatly limits the phase change region when a write current is applied. The result is a high heating efficiency. The top electrode 15 itself can be used to constitute a bit line, or a separate bit line can be provided.

摘要翻译： 非易失性存储元件包括底部电极12; 顶部电极15; 以及包含相变材料的记录层13和可以阻挡设置在底部电极12和顶部电极15之间的记录层13的相变的阻挡层14.阻挡层14由具有电阻的材料构成， 比构成记录层13的材料高。阻挡层14抑制向顶部电极15的热辐射，并且在施加写入电流时极大地限制相变区域。 结果是高的加热效率。 顶部电极15本身可以用于构成位线，或者可以提供单独的位线。

公开(公告)号：US20090221146A1

公开(公告)日：2009-09-03

申请号：US12379772

申请日：2009-02-27

申请人： Akiyoshi Seko ,  Natsuki Sato ,  Isamu Asano

发明人： Akiyoshi Seko ,  Natsuki Sato ,  Isamu Asano

IPC分类号： H01L21/306

CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/128 ,  H01L45/144 ,  H01L45/1675

摘要： The object of the present invention is to provide a manufacturing method for a nonvolatile memory device including a variable resistance having a constricted shape. The nonvolatile memory device of the present invention has a storage section composed of two electrodes and a variable resistance sandwiched between the electrodes. The variable resistance is formed to a constricted shape between the electrodes.

摘要翻译： 本发明的目的是提供一种包括具有收缩形状的可变电阻的非易失性存储装置的制造方法。 本发明的非易失性存储器件具有由两个电极组成的存储部分和夹在电极之间的可变电阻。 可变电阻形成为电极之间的缩小形状。

公开(公告)号：US20080043522A1

公开(公告)日：2008-02-21

申请号：US11666160

申请日：2005-10-25

申请人： Yukio Fuji ,  Isamu Asano ,  Tsuyoshi Kawagoe ,  Kiyoshi Nakai

发明人： Yukio Fuji ,  Isamu Asano ,  Tsuyoshi Kawagoe ,  Kiyoshi Nakai

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  G11C13/0004 ,  G11C2213/78 ,  H01L27/0207 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

摘要： For the purpose of providing a phase change memory device advantageous in layout and operation control by obtaining sufficient write current for high integrated phase change memory devices, the nonvolatile semiconductor memory device of the invention in which word lines and bit lines are arranged in a matrix-shape comprises a select transistor formed at each cross point of the word lines and the bit lines, and a plurality of memory elements commonly connected to the select transistor at one end and connected to a different element select line at an other end and which is capable of writing and reading data. Write and read operations for the selected memory element are controlled by supplying a predetermined current through the select transistor and through the element select line connected to the selected memory element, and the element select lines are arranged in parallel with the bit lines.

摘要翻译： 为了通过获得用于高集成相变存储器件的足够的写入电流来提供有利于布局和操作控制的相变存储器件，本发明的非易失性半导体存储器件，其中字线和位线被布置成矩阵型， 形状包括形成在字线和位线的每个交叉点处的选择晶体管，以及多个存储元件，其一端共同连接到选择晶体管，并且在另一端连接到不同的元件选择线，并且能够 写和读数据。 通过提供预定电流通过选择晶体管并通过连接到所选择的存储元件的元件选择线来控制所选存储元件的写和读操作，并且元件选择线与位线并联布置。

公开(公告)号：US20080042119A1

公开(公告)日：2008-02-21

申请号：US11821246

申请日：2007-06-22

申请人： Regino Sandoval ,  Wolodymyr Czubatyj ,  Tyler Lowrey ,  Isamu Asano

发明人： Regino Sandoval ,  Wolodymyr Czubatyj ,  Tyler Lowrey ,  Isamu Asano

IPC分类号： H01L47/00

CPC分类号： H01L45/1246 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625

摘要： A multi-layer chalcogenide, memory or switching device. The device includes an active region disposed between a first terminal and a second terminal. The active region includes a first layer and a second layer, where one of the layers is a heterogeneous layer that includes an operational component and a promoter component. The other layer may be a homogeneous or heterogeneous layer. In exemplary embodiments, the operational component is a chalcogenide or phase change material and the promoter component is an insulating or dielectric material. Inclusion of the promoter component provides beneficial performance characteristics such as a reduction in reset current or minimization of formation requirements.

摘要翻译： 多层硫族化物，记忆体或开关装置。 该装置包括设置在第一端子和第二端子之间的有源区域。 有源区包括第一层和第二层，其中一层是包含可操作组分和促进剂组分的异质层。 另一层可以是均质或非均质层。 在示例性实施方案中，操作组分是硫族化物或相变材料，并且促进剂组分是绝缘或介电材料。 包含启动子组分提供了有益的性能特征，例如复位电流的降低或形成要求的最小化。

公开(公告)号：US20070096074A1

公开(公告)日：2007-05-03

申请号：US11264129

申请日：2005-11-02

申请人： Isamu Asano ,  Natsuki Sato ,  Tyler Lowrey ,  Guy Wicker ,  Wolodymyr Czubatyj ,  Stephen Hudgens

发明人： Isamu Asano ,  Natsuki Sato ,  Tyler Lowrey ,  Guy Wicker ,  Wolodymyr Czubatyj ,  Stephen Hudgens

IPC分类号： H01L47/00

CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/148

摘要： A non-volatile memory element includes a first interlayer insulation layer 11 having a first through-hole 11a, a second interlayer insulation layer 12 having a second through-hole 12a formed on the first interlayer insulation layer 11, a bottom electrode 13 provided in the first through-hole 11, recording layer 15 containing phase change material provided in the second through-hole 12, a top electrode 16 provided on the second interlayer insulation layer 12, and a thin-film insulation layer 14 formed between the bottom electrode 13 and the recording layer 15. In accordance with this invention, the diameter D1 of a bottom electrode 13 buried in a first through-hole 11a is smaller than the diameter D2 of a second through-hole 12a, thereby decreasing the thermal capacity of the bottom electrode 13. Therefore, when a pore 14a is formed by dielectric breakdown in a thin-film insulation layer 14 and the vicinity is used as a heating region, the amount of heat escaping to the bottom electrode 13 is decreased, resulting in higher heating efficiency.

摘要翻译： 非易失性存储元件包括具有第一通孔11a的第一层间绝缘层11，具有形成在第一层间绝缘层11上的第二通孔12a的第二层间绝缘层12， 在第一通孔11中，设置在第二通孔12中的包含相变材料的记录层15，设置在第二层间绝缘层12上的顶部电极16和形成在第二通孔12的底部电极之间的薄膜绝缘层14 13和记录层15。 根据本发明，埋在第一通孔11a中的底部电极13的直径D 1小于第二通孔12a的直径D 2，从而降低底部电极13的热容量 。 因此，当通过薄膜绝缘层14中的电介质击穿形成孔14a并且将其附近用作加热区域时，逸出到底部电极13的热量减少，导致更高的加热效率。

公开(公告)号：US06987069B2

公开(公告)日：2006-01-17

申请号：US10821842

申请日：2004-04-12

申请人： Yoshikazu Tanabe ,  Isamu Asano ,  Makoto Yoshida ,  Naoki Yamamoto ,  Masayoshi Saito ,  Nobuyoshi Natsuaki

发明人： Yoshikazu Tanabe ,  Isamu Asano ,  Makoto Yoshida ,  Naoki Yamamoto ,  Masayoshi Saito ,  Nobuyoshi Natsuaki

IPC分类号： H01L21/31

CPC分类号： H01L21/28247 ,  H01L21/28061 ,  H01L21/28176 ,  H01L21/32105 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/4941

摘要： With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved.

摘要翻译： 为了防止栅极图案化后的光氧化处理时的金属膜的氧化，同时能够控制氧化膜形成的再现性和栅侧壁端的氧化膜厚度的均匀性 在使用多金属的栅极处理步骤中，通过对已在其上形成有栅极氧化膜的半导体晶片1A上淀积的具有多金属结构的栅电极材料进行构图来形成栅电极， 向被加热到预定温度或附近的半导体晶片1A的主表面供给含有低浓度的水的氢气，由氢和氧通过催化作用形成的水，以选择性地氧化 半导体晶片1A的主表面，从而提高了栅电极的侧壁端部的轮廓。

公开(公告)号：US20050266630A1

公开(公告)日：2005-12-01

申请号：US11196293

申请日：2005-08-04

申请人： Yoshikazu Tanabe ,  Isamu Asano ,  Makoto Yoshida ,  Naoki Yamamoto ,  Masayoshi Saito ,  Nobuyoshi Natsuaki

发明人： Yoshikazu Tanabe ,  Isamu Asano ,  Makoto Yoshida ,  Naoki Yamamoto ,  Masayoshi Saito ,  Nobuyoshi Natsuaki

IPC分类号： H01L29/41 ,  H01L21/28 ,  H01L21/321 ,  H01L21/4763 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/49 ,  H01L29/76 ,  H01L29/78 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H03G3/30 ,  H03M3/02

CPC分类号： H01L21/28247 ,  H01L21/28061 ,  H01L21/28176 ,  H01L21/32105 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823828 ,  H01L21/823857 ,  H01L27/1052 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/4941

摘要： With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved

摘要翻译： 为了在栅极图案化之后防止光氧化处理时的金属膜的氧化，同时可以控制氧化膜形成的再现性和栅极侧壁端的氧化膜厚度的均匀性 在使用多金属的栅极处理步骤中，通过对已在其上形成有栅极氧化膜的半导体晶片1A上淀积的具有多金属结构的栅电极材料进行构图来形成栅电极， 向被加热到预定温度或附近的半导体晶片1A的主表面供给含有低浓度的水的氢气，由氢和氧通过催化作用形成的水，以选择性地氧化 半导体晶片1A的主表面，从而提高了栅电极的侧壁端部的轮廓