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1.发明申请Analog buffer and driving method thereof, liquid crystal display apparatus using the same and driving method thereof 有权模拟缓冲器及其驱动方法，使用其的液晶显示装置及其驱动方法公开(公告)号：US20050007325A1
公开(公告)日：2005-01-13
申请号：US10879346
申请日：2004-06-30
IPC: G09G3/36
CPC classification number: G09G3/3688 , G09G3/3655 , G09G2310/027
Abstract: An analog buffer for buffering an input voltage to an output line is provided. The analog buffer includes a constant current source and a comparator. The constant current source supplies a constant current to the output line, and the comparator compares a voltage charged on the output line with the input voltage to turn-off the constant current source if it is determined that the voltage charged on the output line corresponding to the input voltage is buffered to the output line.
Abstract translation: 提供了用于将输入电压缓冲到输出线的模拟缓冲器。 模拟缓冲器包括恒流源和比较器。 恒定电流源向输出线提供恒定电流，并且比较器将输出线上充电的电压与输入电压进行比较，如果确定在对应于输出线的输出线上充电的电压 输入电压被缓冲到输出线。
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公开(公告)号：US20050142886A1
公开(公告)日：2005-06-30
申请号：US11026288
申请日：2004-12-30
IPC: H01L21/28 , H01L21/302 , H01L21/306 , H01L21/311 , H01L21/461 , H01L21/768
CPC classification number: H01L21/02063 , H01L21/02046 , H01L21/31116 , H01L21/76807 , H01L21/76814
Abstract: A method for forming a contact hole in a semiconductor device is disclosed. The method for forming a contact hole in a semiconductor device comprises depositing a nitride layer and an ILD on a substrate including predetermined devices; forming a first photoresist pattern on the ILD and making a via hole by using the first photoresist pattern; performing a first ashing process; forming a second photoresist pattern on the ILD and making a trench using the second photoresist pattern; conducting a PET; performing a second ashing process and etching the predetermined portion of the nitride layer exposed through the via hole; and wet-cleaning the resulting structure. Accordingly, the present disclosure can fabricate a contact hole maximizing the characteristics of a semiconductor device just by performing a Post Etching Treatment after a trench is formed.
Abstract translation: 公开了一种在半导体器件中形成接触孔的方法。 在半导体器件中形成接触孔的方法包括：在包括预定的器件的衬底上沉积氮化物层和ILD; 在ILD上形成第一光致抗蚀剂图案，并通过使用第一光致抗蚀剂图案形成通孔; 执行第一个灰化过程; 在所述ILD上形成第二光致抗蚀剂图案，并使用所述第二光致抗蚀剂图案形成沟槽; 进行PET; 执行第二灰化处理并蚀刻通过通孔露出的氮化物层的预定部分; 并湿法清洗所得到的结构。 因此，本公开可以仅在通过在形成沟槽之后执行后蚀刻处理来制造使半导体器件的特性最大化的接触孔。
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公开(公告)号：US20060168489A1
公开(公告)日：2006-07-27
申请号：US11044826
申请日：2005-01-26
Applicant: Subhasish Mitra , Ming Zhang , Tak Mak , Quan Shi , Kee Kim
Inventor： Subhasish Mitra , Ming Zhang , Tak Mak , Quan Shi , Kee Kim
IPC: G01R31/28
CPC classification number: G01R31/318541
Abstract: In one embodiment, an apparatus includes a system circuit adapted to generate at a first output terminal a first output signal in response to a data input signal and at least one system clock signal; a shadow circuit adapted to generate at a second output terminal a second output signal in response the data input signal and the at least one system clock signal; and an output joining circuit coupled to at least the first output terminal and the second output terminal.
Abstract translation: 在一个实施例中，一种装置包括适于在第一输出端产生响应于数据输入信号和至少一个系统时钟信号的第一输出信号的系统电路; 阴影电路，其适于在第二输出端产生响应于所述数据输入信号和所述至少一个系统时钟信号的第二输出信号; 以及耦合到至少第一输出端子和第二输出端子的输出接合电路。
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4.发明申请Test pattern of CMOS image sensor and method of measuring process management using the same 失效CMOS图像传感器的测试图案和使用其的测量过程管理方法公开(公告)号：US20070080347A1
公开(公告)日：2007-04-12
申请号：US11545462
申请日：2006-10-11
IPC: H01L23/58
CPC classification number: H01L22/34 , H01L2924/0002 , H01L2924/00
Abstract: The test pattern according to the present invention consists of an opaque metal film pattern formed on a semiconductor substrate, an insulating film formed on the semiconductor substrate and the metal film pattern, a red color filter formed on the insulating film, a planarization layer formed on the insulating film and the red color filter, and a number of micro-lenses formed on the planarization layer.
Abstract translation: 根据本发明的测试图案包括形成在半导体衬底上的不透明金属膜图案，形成在半导体衬底上的绝缘膜和金属膜图案，形成在绝缘膜上的红色滤色器，形成在绝缘膜上的平坦化层 绝缘膜和红色滤色器以及形成在平坦化层上的多个微透镜。
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公开(公告)号：US20070073404A1
公开(公告)日：2007-03-29
申请号：US11341007
申请日：2006-01-27
Applicant: Ralph Rashbaum , Kee Kim , Hyun Bae
Inventor： Ralph Rashbaum , Kee Kim , Hyun Bae
IPC: A61F2/44
CPC classification number: A61F2/4425 , A61B17/0642 , A61B2017/0647 , A61F2/30734 , A61F2/30749 , A61F2002/30331 , A61F2002/30365 , A61F2002/30369 , A61F2002/305 , A61F2002/30576 , A61F2002/30616 , A61F2002/30662 , A61F2002/30878 , A61F2002/30884 , A61F2002/30904 , A61F2002/443 , A61F2220/0016 , A61F2220/0025 , A61F2220/0033
Abstract: The invention relates to an intervertebral disc prosthesis comprising at least two plates, namely first and second plates, articulated about each other by means of a curved surface, namely articulation, of at least one of the plates, each of the plates comprising a surface known as a contact surface, intended to be in contact with a vertebral plate of one of the vertebrae between which the prosthesis is intended to be inserted, this contact surface for each of the plates comprising a geometrical centre at equal distance from at least two diametrically opposite points located on the periphery of the plate, in which the geometric centres of the plates are not vertically aligned, this off-setting of the geometrical centres of the plates engendering an off-setting of the edges of the plates in at least one direction perpendicular to the vertical axis of the spinal column.
Abstract translation: 本发明涉及一种椎间盘假体，其包括至少两个板，即第一和第二板，通过至少一个板的弯曲表面（即铰接）彼此铰接，每个板包括已知的表面 作为接触表面，旨在与要在其中插入假体的椎骨之一的椎板接触，每个板的该接触表面包括与至少两个直径相对的等距离的几何中心 位于板的周边的点，其中板的几何中心不垂直对准，板的几何中心的偏移设计使得板的边缘在垂直于至少一个方向上的偏移设定 到脊柱的垂直轴。
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Patent Agency Ranking
公开(公告)号：US20060005091A1
公开(公告)日：2006-01-05
申请号：US10882523
申请日：2004-06-30
Applicant: Subhasish Mitra , Kee Kim , Tak Mak , Prashant Goteti
Inventor： Subhasish Mitra , Kee Kim , Tak Mak , Prashant Goteti
IPC: G01R31/28
CPC classification number: G01R31/318541 , G01R31/31816 , G01R31/318566 , G11C2029/3202
Abstract: In one embodiment, an apparatus includes a datapath circuit to generate a data output signal in response to a data input signal and at least a first data clock signal; a shadow circuit, coupled to the datapath circuit, to generate a shadow output signal in response the data input signal and at least a second data clock signal during a functional mode of operation and to generate a scan-out signal in response to a scan-in signal and at least a first test clock signal during a test mode of operation; and an error detect circuit, coupled to the datapath and the shadow circuits, to generate an error signal in response to a mismatch between the data output signal and the shadow output signal.
Abstract translation: 在一个实施例中，一种装置包括数据路径电路，用于响应于数据输入信号和至少第一数据时钟信号而产生数据输出信号; 阴影电路，耦合到数据路径电路，以在功能操作模式期间响应于数据输入信号和至少第二数据时钟信号产生阴影输出信号，并且响应于扫描信号产生扫描输出信号， 在测试操作模式期间的信号和至少第一测试时钟信号; 以及耦合到数据路径和阴影电路的误差检测电路，以响应于数据输出信号和阴影输出信号之间的失配而产生误差信号。
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7.发明申请公开(公告)号：US20070162130A1
公开(公告)日：2007-07-12
申请号：US11362253
申请日：2006-02-24
Applicant: Ralph Rashbaum , Kee Kim , Hyun Bae , Jean-Paul Steib
Inventor： Ralph Rashbaum , Kee Kim , Hyun Bae , Jean-Paul Steib
IPC: A61F2/44
CPC classification number: A61F2/4425 , A61F2/4611 , A61F2002/30235 , A61F2002/30365 , A61F2002/30369 , A61F2002/30512 , A61F2002/30601 , A61F2002/30616 , A61F2002/30649 , A61F2002/30662 , A61F2002/30841 , A61F2002/30878 , A61F2002/30884 , A61F2002/30904 , A61F2002/443 , A61F2002/4475 , A61F2002/4622 , A61F2002/4627 , A61F2002/4628 , A61F2220/0025 , A61F2220/0033 , A61F2230/0069 , Y10S606/914
Abstract: The present invention relates to an intervertebral disc prosthesis and insertion instrumentation, the prosthesis comprising at least first and second osseous anchoring means, the first osseous anchoring means disposed proximal to the periphery of the plate on which it is situated and the second osseous anchoring means being offset along the antero-posterior axis, the second osseous anchoring means comprising a basal portion and a sharp-edged portion of width narrower than the basal portion. The instrumentation comprises a rod fitted with at least two feet forming a clip and sliding in a tube, sliding the rod in the tube, in the direction of the manipulation end, causing closing of the clip by contact between the exterior of the feet and a truncated portion of the tube and sliding the rod in the tube, in the direction of the prehension end, causing opening of the clip by contact between an axis and the interior of the feet of the rod.
Abstract translation: 本发明涉及椎间盘假体和插入器械，所述假体包括至少第一和第二骨锚固装置，所述假体包括至少第一和第二骨锚固装置，所述第一骨锚固装置邻近所述板的周边设置，所述第二骨锚固装置 沿着前后轴偏移，第二骨锚固装置包括基部和宽度比基部窄的尖锐边缘部分。 仪器包括装配有至少两个脚的杆，其形成夹子并且在管中滑动，沿着操作端的方向在管中滑动杆，从而通过脚的外部和外部之间的接触闭合夹子 管的截头部分并且沿着预防端的方向在管中滑动杆，从而通过轴线和杆的内部之间的接触来打开夹子。
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公开(公告)号：US20050087746A1
公开(公告)日：2005-04-28
申请号：US10691055
申请日：2003-10-22
Applicant: Olga Kryliouk , Tim Anderson , Omar Bchir , Kee Kim
Inventor： Olga Kryliouk , Tim Anderson , Omar Bchir , Kee Kim
IPC: H01L21/20 , H01L21/205 , H01L27/15 , H01L33/00 , H01L33/12
CPC classification number: H01L33/12 , H01L21/02381 , H01L21/02461 , H01L21/0254 , H01L21/0262 , H01L21/02661 , H01L33/007
Abstract: A semiconductor device and method for forming the same includes a silicon (111) single crystal substrate, and an epitaxial boron phosphide (BP) layer disposed on the substrate. A group III-nitride semiconductor epitaxial layer is disposed on the BP epitaxial layer.
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公开(公告)号：US20050001799A1
公开(公告)日：2005-01-06
申请号：US10875733
申请日：2004-06-25
Applicant: Kee Kim
Inventor： Kee Kim
IPC: G09G3/36
CPC classification number: G09G3/3688 , G09G3/3696 , G09G2310/027 , G09G2310/0291 , G09G2330/021
Abstract: An analog buffer circuit for a liquid crystal display (LCD) device includes a first capacitor and an inverter connected in series between an input terminal and an output terminal, a first reset switch connected between the input terminal and the first capacitor to reset the first capacitor, a first feedback switch connected to a first node between the first capacitor and the first reset switch, a second capacitor and a second feedback switch connected in series between a second node and a third node, the second node connected between the first capacitor and the inverter, and the third node connected between the inverter and the output terminal, a second reset switch connected between the second node and the third node to reset the inverter, and a third reset switch connected to a fourth node between the second capacitor and the second feedback switch to reset the second capacitor.
Abstract translation: 一种用于液晶显示器（LCD）器件的模拟缓冲电路，包括串联连接在输入端和输出端之间的第一电容器和反相器，连接在输入端和第一电容器之间的第一复位开关，以复位第一电容器 连接到第一电容器和第一复位开关之间的第一节点的第一反馈开关，串联连接在第二节点和第三节点之间的第二电容器和第二反馈开关，第二节点连接在第一电容器和第二电容器之间， 逆变器和连接在逆变器和输出端子之间的第三节点，连接在第二节点和第三节点之间的第二复位开关以复位反相器;以及第三复位开关，连接到第二电容器和第二电容器之间的第四节点 反馈开关复位第二个电容。
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公开(公告)号：US20080024372A1
公开(公告)日：2008-01-31
申请号：US11647022
申请日：2006-12-28
IPC: H01Q1/24
Abstract: A dual band antenna unit for a mobile device may include an antenna receiving part, a first antenna part having a first contact point and a second contact point, a second antenna part, a first feed point and a second feed point. The second antenna part may be formed integrally with the first antenna part and may extend from the first antenna part. The second antenna part may be extractably and retractably mounted in the mobile device. The first antenna part and the second antenna part may have resonant frequencies of different frequency bands. When the second antenna part is extracted, the first contact point may contact the first feed point. When the second antenna part is retracted, the second contact point may contact the second feed point. The mobile device may operate in different frequency bands using a single antenna unit, thereby allowing freedom of internal design and meeting the demand for miniaturization.
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