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    Capacitor structure for two-transistor DRAM memory cell and method of forming same
    1.
    发明授权
    Capacitor structure for two-transistor DRAM memory cell and method of forming same 有权
    双晶体管DRAM存储单元的电容结构及其形成方法

    公开(公告)号：US07488664B2

    公开(公告)日：2009-02-10

    申请号：US11200667

    申请日：2005-08-10

    Applicant: Keith Cook ,  Ceredig Roberts

    Inventor： Keith Cook ,  Ceredig Roberts

    IPC: H01L21/20

    CPC classification number: H01L28/90 ,  H01L27/10852 ,  H01L28/82

    Abstract: A capacitor structure for a semiconductor assembly and a method for forming same are described. The capacitor structure comprises a pair of electrically separated capacitor electrodes and a capacitor electrode being common to only the pair of electrically separated capacitor electrodes.

    Abstract translation: 描述了用于半导体组件的电容器结构及其形成方法。 电容器结构包括一对电隔离的电容器电极和仅对一对电隔离的电容器电极共同的电容器电极。

    Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fabricating integrated circuitry
    4.
    发明申请
    Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fabricating integrated circuitry 有权

    公开(公告)号：US20060223279A1

    公开(公告)日：2006-10-05

    申请号：US11097876

    申请日：2005-04-01

    Applicant: Robert Patraw ,  M. Roberts ,  Keith Cook

    Inventor： Robert Patraw ,  M. Roberts ,  Keith Cook

    IPC: H01L21/76

    CPC classification number: H01L21/76229

    Abstract: First and second isolation trenches are formed into semiconductive material of a semiconductor substrate. The first isolation trench has a narrowest outermost cross sectional dimension which is less than that of the second isolation trench. An insulative layer is deposited to within the first and second isolation trenches effective to fill remaining volume of the first isolation trench within the semiconductive material but not that of the second isolation trench within the semiconductive material. The insulative layer comprises silicon dioxide deposited from flowing TEOS to the first and second isolation trenches. A spin-on-dielectric is deposited over the silicon dioxide deposited from flowing the TEOS within the second isolation trench within the semiconductive material, but not within the first isolation trench within the semiconductive material. The spin-on-dielectric is deposited effective to fill remaining volume of the second isolation trench within the semiconductive material. The spin-on-dielectric is densified within the second isolation trench.

    Methods of forming protective segments of material, and etch stops
    5.
    发明授权
    Methods of forming protective segments of material, and etch stops 有权

    公开(公告)号：US06653241B2

    公开(公告)日：2003-11-25

    申请号：US10098680

    申请日：2002-03-12

    Applicant: Mark E. Jost ,  Keith Cook ,  Erik Byers

    Inventor： Mark E. Jost ,  Keith Cook ,  Erik Byers

    IPC: H01L21302

    CPC classification number: H01L27/10855 ,  H01L21/31116 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10888 ,  H01L28/90

    Abstract: The invention encompasses a method of forming a protective segment of material. A plurality of at least three conductive lines are provided over a semiconductor substrate. A material is formed over the conductive lines, and a patterned masking layer is formed to cover a segment of the material extending between a pair of the conductive lines while leaving another segment of the material uncovered. The uncovered segment of the material is anisotropically etched to form separated spacers from the uncovered segment. The separated spacers are along sidewalls of at least two of the conductive lines. The covered segment of the material remains after the anisotropic etching, and is a protective segment of the material over the semiconductor substrate.

    Methods of forming protective segments of material, and etch stops
    7.
    发明授权
    Methods of forming protective segments of material, and etch stops 有权
    形成材料保护段的方法和蚀刻停止

    公开(公告)号：US06620734B1

    公开(公告)日：2003-09-16

    申请号：US10283774

    申请日：2002-10-29

    Applicant: Mark E. Jost ,  Keith Cook ,  Erik Byers

    Inventor： Mark E. Jost ,  Keith Cook ,  Erik Byers

    IPC: H01L21311

    CPC classification number: H01L27/10855 ,  H01L21/31116 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/10888 ,  H01L28/90

    Abstract: The invention encompasses a method of forming a protective segment of material. A plurality of at least three conductive lines are provided over a semiconductor substrate. A material is formed over the conductive lines, and a patterned masking layer is formed to cover a segment of the material extending between a pair of the conductive lines while leaving another segment of the material uncovered. The uncovered segment of the material is anisotropically etched to form separated spacers from the uncovered segment. The separated spacers are along sidewalls of at least two of the conductive lines. The covered segment of the material remains after the anisotropic etching, and is a protective segment of the material over the semiconductor substrate.

    Abstract translation: 本发明包括形成材料的保护段的方法。 在半导体衬底上提供多条至少三条导线。 在导电线上形成材料，并且形成图案化的掩模层以覆盖在一对导电线之间延伸的材料的一部分，同时留下未覆盖的材料的另一部分。 材料的未覆盖部分被各向异性地蚀刻以从未覆盖部分形成分离的间隔物。 分离的间隔物沿着至少两条导电线的侧壁。 材料的覆盖段在各向异性蚀刻之后保留，并且是半导体衬底上材料的保护段。

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