公开(公告)号：US4148775A

公开(公告)日：1979-04-10

申请号：US897186

申请日：1978-04-17

申请人： Keizo Shima ,  Yuichi Harada ,  Yoshinobu Ohya

发明人： Keizo Shima ,  Yuichi Harada ,  Yoshinobu Ohya

IPC分类号： C08G61/02 ,  C09J177/00 ,  C08K5/36 ,  C08L77/00

CPC分类号： C08G61/02 ,  C09J177/00

摘要： A novel hot-melt adhesive composition comprising 100 parts by weight of a polyamide copolymer resin having a melting point of about 80.degree. to about 160.degree. C. and composed of at least three monomers, about 5 to about 30 parts by weight of a terpene-phenol resin having a softening point of about 80.degree. to about 120.degree. C., and about 5 to about 10 parts by weight of a plasticizer.

摘要翻译： 一种新型热熔粘合剂组合物，其包含100重量份的熔点为约80至约160℃的聚酰胺共聚物树脂，并由至少三种单体组成，约5至约30重量份的萜烯 酚树脂，其软化点为约80至约120℃，和约5至约10重量份的增塑剂。

公开(公告)号：US4137366A

公开(公告)日：1979-01-30

申请号：US756839

申请日：1977-01-05

申请人： Yuichi Harada ,  Yoshinobu Ohya

发明人： Yuichi Harada ,  Yoshinobu Ohya

IPC分类号： B60R13/02 ,  B29C63/00 ,  B32B27/08 ,  B32B27/34 ,  C08J5/12 ,  C09J177/00 ,  B32B5/18 ,  B32B17/10 ,  B32B31/04

CPC分类号： B29C63/0017 ,  B32B27/08 ,  B60R13/02 ,  Y10T428/24488 ,  Y10T428/31562 ,  Y10T428/3158 ,  Y10T428/31739

摘要： A laminate for interior finish material comprising a frame and a covering material thermally adhered to each other with a hot melt adhesive containing a polyamide copolymer of a melting point of about 80.degree. - 140.degree. C as principal component.

摘要翻译： 一种用于内部装饰材料的层压材料，其包括用包含熔点为约80-140℃的聚酰胺共聚物作为主要组分的热熔粘合剂彼此热粘合的框架和覆盖材料。

公开(公告)号：US3997625A

公开(公告)日：1976-12-14

申请号：US611208

申请日：1975-09-08

申请人： Ken Ando ,  Yuichi Harada ,  Yoshinobu Ohya

发明人： Ken Ando ,  Yuichi Harada ,  Yoshinobu Ohya

IPC分类号： C09J177/00 ,  C08L77/02

CPC分类号： C09J177/00

摘要： A thermoplastic hot melt adhesive composition for bonding metals which comprises a homogeneous mixture of (A) 60 to 90 percent by weight of a nylon material selected from the group consisting of homopolymers and copolymers of nylon monomer selected from the group consisting of nylon salts having at least 10 carbon atoms, nylon-forming .omega.-amino acids and nylon-forming lactams, and (B) 10 to 40 percent by weight of an ethylene/vinyl acetate copolymer containing 1 to 25 weight percent of vinyl acetate.

摘要翻译： 一种用于接合金属的热塑性热熔粘合剂组合物，其包含（A）60-90％重量的尼龙材料的均匀混合物，所述尼龙材料选自尼龙单体的均聚物和共聚物，所述尼龙单体选自尼龙盐，所述尼龙盐具有 至少10个碳原子，形成尼纶的氨基酸和形成尼龙的内酰胺，和（B）10至40重量％的含有1至25重量％乙酸乙烯酯的乙烯/乙酸乙烯酯共聚物。

公开(公告)号：US20070029636A1

公开(公告)日：2007-02-08

申请号：US11420779

申请日：2006-05-29

申请人： Hiroshi Kanemaru ,  Naoki Kumagai ,  Yuichi Harada ,  Yoshihiro Ikura ,  Yoshiaki Minoya

发明人： Hiroshi Kanemaru ,  Naoki Kumagai ,  Yuichi Harada ,  Yoshihiro Ikura ,  Yoshiaki Minoya

IPC分类号： H01L29/00

CPC分类号： H01L21/76283 ,  H01L21/76275 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78603

摘要： The shape of a tip of an insulating material of an insulating isolation region is provided as being a concave one recessed below the back surface of an n-semiconductor substrate. This reduces the electric field strength at the corner at which the bottom of the n-semiconductor substrate is in contact with the insulating isolation region to allow an excellent breakdown voltage to be obtained. Moreover, by forming a high impurity concentration region such as a field-stop layer on the back surface of the n-semiconductor substrate, a depletion layer extending from the top surface is prevented from reaching the back surface This eliminates an influence of a surface state introduced in the interface between the insulator film formed on the back surface and the n-semiconductor substrate, by which an excellent breakdown voltage can be obtained.

摘要翻译： 绝缘隔离区域的绝缘材料的顶端的形状设置为在n半导体衬底的背面下方凹入的凹部。 这降低了在半导体衬底的底部与绝缘隔离区接触的拐角处的电场强度，以获得优异的击穿电压。 此外，通过在n半导体衬底的背面上形成诸如场阻止层的高杂质浓度区域，可以防止从顶面延伸的耗尽层到达后表面。这消除了表面状态的影响 引入到形成在背面的绝缘体膜与n半导体衬底之间的界面中，由此可以获得优异的击穿电压。

公开(公告)号：US5914503A

公开(公告)日：1999-06-22

申请号：US798743

申请日：1997-02-13

申请人： Noriyuki Iwamuro ,  Yuichi Harada

发明人： Noriyuki Iwamuro ,  Yuichi Harada

IPC分类号： H01L29/74 ,  H01L29/745 ,  H01L29/749 ,  H01L31/111

CPC分类号： H01L29/749 ,  H01L29/7455

摘要： An insulated gate thyristor is provided in which an inversion layer is created beneath a gate electrode to which a voltage is applied. An emitter region of a first conductivity type is biased to the same potential as a first main electrode via a MOSFET channel, and a thyristor portion consisting of the emitter region, a second base region of a second conductivity type, a base layer of the first conductivity type and an emitter layer of the second conductivity type is turned on. As electrons are injected uniformly from the entire emitter region, the insulated gate thyristor quickly shifts to the thyristor mode, and the on-voltage of the insulated gate thyristor of the invention is lowered. The insulated gate thyristor of the invention does not require a hole current that flows through the second base region of a convention EST in the Z-direction. In turning off, the pn junction recovers quickly without causing current localization, and the breakdown withstand capability if improved.

摘要翻译： 提供一种绝缘栅极晶闸管，其中在施加电压的栅电极下面形成反型层。 第一导电类型的发射极区域经由MOSFET沟道被偏置到与第一主电极相同的电位，并且由发射极区域，第二导电类型的第二基极区域，第一导电类型的基极层 导电类型和第二导电类型的发射极层导通。 由于电子从整个发射极区均匀注入，所以绝缘栅极晶闸管迅速转移到晶闸管模式，并且本发明的绝缘栅晶闸管的导通电压降低。 本发明的绝缘栅极晶闸管不需要在常规EST的Z方向上流过第二基极区域的空穴电流。 在关闭时，pn结快速恢复，而不会导致电流定位，如果改进，击穿耐受能力。

公开(公告)号：US4818130A

公开(公告)日：1989-04-04

申请号：US121880

申请日：1987-11-17

申请人： Yuichi Harada ,  Hajime Kumazawa

发明人： Yuichi Harada ,  Hajime Kumazawa

IPC分类号： B41J29/36

CPC分类号： B41J29/36

摘要： A character erasable printing apparatus is designed to erase a character or an underline in plural times of erasing action by moving the printing head, and to print a character by a single printing action.Therefore, when an underlined character is erased together with its underline, and a correct character is printed together with an underline, the underline is interrupted.Disclosed are, to pervent such interruption of the underline, a character erasable printing apparatus capable of erasing only the character without erasing the underline when the underline mode is being set, a character erasable printing apparatus capable of erasing only the character without erasing the underline when erasing a character adjacent to an underlined character, and a character erasable printing apparatus capable of erasing the underline without moving the printing head when erasing an underline of a character adjacent to an underlined character.

摘要翻译： 字符可擦除打印设备被设计为通过移动打印头来擦除多次擦除动作中的字符或下划线，并且通过单次打印动作来打印字符。 因此，当下划线字符与下划线一起删除时，正确的字符与下划线一起打印，下划线中断。 公开了为了防止下划线的这种中断，可以在下划线模式被设置时能够仅擦除字符而不擦除下划线的字符可擦除打印设备，能够仅擦除字符而不擦除下划线的字符可擦除打印设备 擦除与下划线字符相邻的字符，以及字符可擦除打印设备，当擦除与下划线字符相邻的字符的下划线时，能够擦除下划线而不移动打印头。

公开(公告)号：US20140008666A1

公开(公告)日：2014-01-09

申请号：US14006548

申请日：2012-04-06

申请人： Yuichi Harada ,  Shinsuke Harada ,  Yasuyuki Hoshi ,  Noriyuki Iwamuro

发明人： Yuichi Harada ,  Shinsuke Harada ,  Yasuyuki Hoshi ,  Noriyuki Iwamuro

IPC分类号： H01L29/06 ,  H01L29/78

CPC分类号： H01L29/0615 ,  H01L29/0626 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/7802 ,  H01L29/7808 ,  H01L29/7827

摘要： A silicon carbide vertical field effect transistor includes a first-conductive-type silicon carbide substrate; a low-concentration first-conductive-type silicon carbide layer formed on a surface of the first-conductive-type silicon carbide substrate; second-conductive-type regions selectively formed on a surface of the first-conductive-type silicon carbide layer; first-conductive-type source regions formed in the second-conductive-type regions; a high-concentration second-conductive-type region formed between the first-conductive-type source regions in the second-conductive-type region; a source electrode electrically connected to the high-concentration second-conductive-type region and a first-conductive-type source region; a gate insulating film formed from the first-conductive-type source regions formed in adjacent second-conductive-type regions, onto the second-conductive-type regions and the first-conductive-type silicon carbide layer; a gate electrode formed on the gate insulating film; and a drain electrode on the back side of the first-conductive-type silicon carbide substrate, wherein an avalanche generating unit is disposed between the second-conductive-type region and the first-conductive-type silicon carbide layer.

摘要翻译： 碳化硅垂直场效应晶体管包括第一导电型碳化硅衬底; 形成在第一导电型碳化硅衬底的表面上的低浓度第一导电型碳化硅层; 选择性地形成在第一导电型碳化硅层的表面上的第二导电型区域; 形成在第二导电型区域中的第一导电型源极区域; 形成在第二导电型区域中的第一导电型源极区域之间的高浓度第二导电型区域; 与高浓度第二导电型区域电连接的源电极和第一导电型源极区域; 由形成在相邻的第二导电型区域的第一导电型源极区域形成在第二导电型区域和第一导电型碳化硅层上的栅极绝缘膜; 形成在栅极绝缘膜上的栅电极; 以及在第一导电型碳化硅衬底的背侧上的漏电极，其中雪崩产生单元设置在第二导电型区域和第一导电型碳化硅层之间。

公开(公告)号：US07723817B2

公开(公告)日：2010-05-25

申请号：US11420779

申请日：2006-05-29

申请人： Hiroshi Kanemaru ,  Naoki Kumagai ,  Yuichi Harada ,  Yoshihiro Ikura ,  Yoshiaki Minoya

发明人： Hiroshi Kanemaru ,  Naoki Kumagai ,  Yuichi Harada ,  Yoshihiro Ikura ,  Yoshiaki Minoya

IPC分类号： H01L29/00

CPC分类号： H01L21/76283 ,  H01L21/76275 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78603

摘要： The shape of a tip of an insulating material of an insulating isolation region is provided as being a concave one recessed below the back surface of an n-semiconductor substrate. This reduces the electric field strength at the corner at which the bottom of the n-semiconductor substrate is in contact with the insulating isolation region to allow an excellent breakdown voltage to be obtained. Moreover, by forming a high impurity concentration region such as a field-stop layer on the back surface of the n-semiconductor substrate, a depletion layer extending from the top surface is prevented from reaching the back surface. This eliminates an influence of a surface state introduced in the interface between the insulator film formed on the back surface and the n-semiconductor substrate, by which an excellent breakdown voltage can be obtained.

摘要翻译： 绝缘隔离区域的绝缘材料的顶端的形状设置为在n半导体衬底的背面下方凹入的凹部。 这降低了在半导体衬底的底部与绝缘隔离区接触的拐角处的电场强度，以获得优异的击穿电压。 此外，通过在n半导体衬底的背面上形成诸如场阻止层的高杂质浓度区域，可以防止从顶面延伸的耗尽层到达背面。 这消除了在形成在背面的绝缘体膜与n型半导体衬底之间的界面中引入的表面状态的影响，由此可获得优异的击穿电压。

公开(公告)号：US06278140B1

公开(公告)日：2001-08-21

申请号：US09511167

申请日：2000-02-24

申请人： Yuichi Harada ,  Noriyuki Iwamuro ,  Tadayoshi Iwaana

发明人： Yuichi Harada ,  Noriyuki Iwamuro ,  Tadayoshi Iwaana

IPC分类号： H01L2974

CPC分类号： H01L29/0692 ,  H01L29/7455 ,  H01L29/749

摘要： An insulated gate thyristor is provided which includes: a first-conductivity-type base layer, first and second-conductivity-type base regions formed in the base layer, a first-conductivity-type source region formed in the first base region, a first-conductivity-type emitter region formed in the second base region, and a gate electrode layer formed on a gate insulating film over the first base region, first-conductivity-type base layer, and second base region, which are interposed between the first-conductivity-type source region and the first-conductivity-type emitter region. The thyristor further includes a first main electrode that contacts with both the first base region and the first-conductivity-type source region, a second-conductivity-type emitter layer formed on the other surface of the first-conductivity-type base layer, a second main electrode that contacts with the second-conductivity-type emitter layer, a gate electrode connected to the gate electrode layer; and an insulating film covering entire surface areas of the second second-conductivity-type base region and the first-conductivity-type emitter region. In this insulated gate thyristor, an exposed surface portion of the first second-conductivity-type base region that is interposed between the first-conductivity-type base layer and the first-conductivity-type source region has a smaller width than an exposed surface portion of the second second-conductivity-type base region interposed between the first-conductivity-type base layer and the first-conductivity-type emitter region.

摘要翻译： 提供了一种绝缘栅极晶闸管，其包括：第一导电型基极层，形成在基极层中的第一和第二导电型基极区域，形成在第一基极区域中的第一导电型源极区域， 形成在第二基极区域中的导电型发射极区域和形成在第一基极区域上的栅极绝缘膜上的栅电极层，第一导电型基极层和第二基极区域， 导电型源极区域和第一导电型发射极区域。 晶闸管还包括与第一基极区域和第一导电型源极区域接触的第一主电极，形成在第一导电型基极层的另一个表面上的第二导电型发射极层， 与第二导电型发射极层接触的第二主电极，连接到栅电极层的栅电极; 以及覆盖所述第二第二导电型基极区域和所述第一导电型发射极区域的整个表面区域的绝缘膜。 在该绝缘栅极晶闸管中，介于第一导电型基极层和第一导电型源极区域之间的第一第二导电型基极区域的露出面部分的宽度比露出面部分 位于第一导电型基极层和第一导电型发射极区域之间的第二第二导电型基极区域。

公开(公告)号：US6091087A

公开(公告)日：2000-07-18

申请号：US852269

申请日：1997-05-06

申请人： Noriyuki Iwamuro ,  Yuichi Harada ,  Tadayoshi Iwaana

发明人： Noriyuki Iwamuro ,  Yuichi Harada ,  Tadayoshi Iwaana

IPC分类号： H01L29/745 ,  H01L29/749 ,  H01L29/74 ,  H01L29/00

CPC分类号： H01L29/7455 ,  H01L29/749

摘要： An insulated gate thyristor includes a first-conductivity-type base layer having a high resistivity, first and second second-conductivity-type base regions formed in a surface layer of the first-conductivity-type base layer, a first-conductivity-type source region formed in a surface layer of the first second-conductivity-type base region, and a first-conductivity-type emitter region formed in a surface layer of the second second-conductivity-type base region. The thyristor further includes a gate electrode formed through an insulating film on the first second-conductivity-type base region, an exposed portion of the first-conductivity-type base layer and the second second-conductivity-type base region, a first main electrode that contacts both the first second-conductivity-type base layer and first-conductivity-type source region, a second-conductivity-type emitter layer formed on the first-conductivity-type base layer, a second main electrode that contacts the second-conductivity-type emitter layer, and an insulating film covering entire areas of surfaces of the second second-conductivity-type base region and first-conductivity-type emitter region. The second second-conductivity-type base region has a diffusion depth that is greater than a larger one of diffusion depths of the first second-conductivity-type base region and a second-conductivity-type well region included in the first second-conductivity-type base region.

摘要翻译： 绝缘栅晶闸管包括第一导电型基极层，其具有形成在第一导电型基极层的表面层中的高电阻率，第一和第二第二导电型基极区域，第一导电型源极 形成在第一第二导电型基极区域的表面层中的第一导电型发射极区域和形成在第二第二导电型基极区域的表面层中的第一导电型发射极区域。 晶闸管还包括通过第一第二导电型基极区域上的绝缘膜形成的栅电极，第一导电型基极层和第二第二导电型基极区域的露出部分，第一主电极 其与第一导电型基极层和第一导电型源极区域接触，形成在第一导电型基极层上的第二导电型发射极层，与第二导电型基极层接触的第二主电极 型发射极层和覆盖第二第二导电型基极区域和第一导电型发射极区域的整个表面的绝缘膜。 所述第二第二导电型基区具有比所述第一第二导电型基区的扩散深度大的扩散深度和包含在所述第一第二导电型基极区中的第二导电型阱区的扩散深度。 型基地区。