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公开(公告)号：US20110169015A1
公开(公告)日：2011-07-14
申请号：US13060697
申请日：2009-08-25
申请人： Yuki Negoro , Akihiko Horiuchi , Kensuke Iwanaga , Seiichi Yokoyama , Hideki Hashimoto , Kenichi Nonaka , Yusuke Maeyama , Masashi Sato , Masaaki Shimizu
发明人： Yuki Negoro , Akihiko Horiuchi , Kensuke Iwanaga , Seiichi Yokoyama , Hideki Hashimoto , Kenichi Nonaka , Yusuke Maeyama , Masashi Sato , Masaaki Shimizu
IPC分类号： H01L29/161 , H01L21/56
CPC分类号： H01L29/732 , H01L23/3171 , H01L23/3192 , H01L29/045 , H01L29/1608 , H01L29/42304 , H01L29/6606 , H01L29/66068 , H01L29/6609 , H01L29/66295 , H01L29/66416 , H01L29/7722 , H01L29/8613 , H01L2224/06181 , H01L2924/1305 , H01L2924/13062 , H01L2924/13091 , H01L2924/00
摘要： Disclosed is a bipolar semiconductor device which is capable of reducing the surface state density of a bipolar transistor and increasing the current gain of the transistor, thereby improving the transistor performance. A bipolar semiconductor device (100) has a surface protective film (30) on the surface of a semiconductor element. The surface protective film is composed of a thermal oxide film (31) formed on the surface of the semiconductor element, and a deposited oxide film (32) formed on the thermal oxide film. The deposited oxide film contains at least one of hydrogen element and nitrogen element in an amount of not less than 1018 cm−3.
摘要翻译： 公开了能够降低双极晶体管的表面状态密度并增加晶体管的电流增益的双极半导体器件，从而提高晶体管的性能。 双极半导体器件（100）在半导体元件的表面上具有表面保护膜（30）。 表面保护膜由形成在半导体元件的表面上的热氧化膜（31）和形成在热氧化膜上的沉积氧化物膜（32）构成。 沉积的氧化物膜含有不少于1018cm-3的氢元素和氮元素中的至少一种。
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公开(公告)号：US07544552B2
公开(公告)日：2009-06-09
申请号：US11386661
申请日：2006-03-23
申请人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Kensuke Iwanaga , Yoshimitsu Saito , Hiroaki Iwakuro , Masaaki Shimizu , Yusuke Fukuda , Koichi Nishikawa , Yusuke Maeyama
发明人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Kensuke Iwanaga , Yoshimitsu Saito , Hiroaki Iwakuro , Masaaki Shimizu , Yusuke Fukuda , Koichi Nishikawa , Yusuke Maeyama
IPC分类号： H01L21/337 , H01L29/772 , H01L21/339 , H01L21/338 , H01L29/768 , H01L29/78
CPC分类号： H01L29/7722
摘要： A method for manufacturing a junction semiconductor device, having a step for forming a first high-resistance layer, a step for forming a channel-doped layer, a step for forming a second high-resistance layer, a step for forming a low-resistance layer of a first conductive type that acts as a source region, a step for performing partial etching to a midway depth of the second high-resistance layer and the low-resistance layer, a step for forming a gate region below the portion etched in the etching step, and a step for forming a protective film on the surface of the region between the gate region and the source region. A gate region is formed using relatively low energy ion implantation in the surface that has been etched in advance to a height that is between the lower surface of the source area and the upper surface of the channel-doped layer.
摘要翻译： 一种用于制造具有形成第一高电阻层的步骤的接合半导体器件的制造方法，形成沟道掺杂层的步骤，用于形成第二高电阻层的步骤，形成低电阻的步骤 作为源极区域的第一导电类型的层，用于对第二高电阻层和低电阻层的中间深度进行部分蚀刻的步骤，用于在第二高电阻层和低电阻层的蚀刻部分的下方形成栅极区域的步骤 蚀刻步骤，以及在栅极区域和源极区域之间的区域的表面上形成保护膜的步骤。 在表面中使用相对较低能量的离子注入，预先将蚀刻的源极区域的下表面和沟道掺杂层的上表面之间的高度形成为栅极区域。
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公开(公告)号：US20060216879A1
公开(公告)日：2006-09-28
申请号：US11386661
申请日：2006-03-23
申请人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Kensuke Iwanaga , Yoshimitsu Saito , Hiroaki Iwakuro , Masaaki Shimizu , Yusuke Fukuda , Koichi Nishikawa , Yusuke Maeyama
发明人： Ken-ichi Nonaka , Hideki Hashimoto , Seiichi Yokoyama , Kensuke Iwanaga , Yoshimitsu Saito , Hiroaki Iwakuro , Masaaki Shimizu , Yusuke Fukuda , Koichi Nishikawa , Yusuke Maeyama
IPC分类号： H01L21/337
CPC分类号： H01L29/7722
摘要： A method for manufacturing a junction semiconductor device, having a step for forming a first high-resistance layer, a step for forming a channel-doped layer, a step for forming a second high-resistance layer, a step for forming a low-resistance layer of a first conductive type that acts as a source region, a step for performing partial etching to a midway depth of the second high-resistance layer and the low-resistance layer, a step for forming a gate region below the portion etched in the etching step, and a step for forming a protective film on the surface of the region between the gate region and the source region. A gate region is formed using relatively low energy ion implantation in the surface that has been etched in advance to a height that is between the lower surface of the source area and the upper surface of the channel-doped layer.
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4.发明申请ELECTRODE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE 审中-公开电极，半导体器件及制造半导体器件的方法公开(公告)号：US20110198617A1
公开(公告)日：2011-08-18
申请号：US13125187
申请日：2009-10-06
申请人： Kensuke Iwanaga , Seiichi Yokoyama , Hideki Hashimoto , Kenichi Nonaka , Masashi Sato , Norio Tsuyuguchi
发明人： Kensuke Iwanaga , Seiichi Yokoyama , Hideki Hashimoto , Kenichi Nonaka , Masashi Sato , Norio Tsuyuguchi
IPC分类号： H01L29/20 , H01L21/283 , B82Y99/00 , B82Y40/00
CPC分类号： H01L21/0485 , H01L21/28512 , H01L23/485 , H01L29/1608 , H01L29/6606 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a semiconductor device comprising a p-type SiC semiconductor and an ohmic electrode having an Ni/Al laminated structure provided on the p-type SiC semiconductor. The semiconductor device simultaneously has improved contact resistance and surface roughness in the ohmic electrode. The semiconductor device comprises an ohmic electrode (18) comprising a nickel (Ni) layer (21), a titanium (Ti) layer (22), and an aluminum (Al) layer (23) stacked in that order on a p-type silicon carbide semiconductor region (13). The ohmic electrode (18) comprises 14 to 47 atomic % of a nickel element, 5 to 12 atomic % of titanium element, and 35 to 74 atomic % of an aluminum element, provided that the atomic ratio of the nickel element to the titanium element is 1 to 11.
摘要翻译： 公开了一种包括p型SiC半导体和在p型SiC半导体上设置有Ni / Al层叠结构的欧姆电极的半导体器件。 半导体器件同时具有改善的欧姆电极中的接触电阻和表面粗糙度。 该半导体器件包括欧姆电极（18），其包括镍（Ni）层（21），钛（Ti）层（22）和铝（Al）层（23），其依次堆叠在p型 碳化硅半导体区域（13）。 欧姆电极（18）包含14至47原子％的镍元素，5至12原子％的钛元素和35至74原子％的铝元素，条件是镍元素与钛元素的原子比 是1到11。
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公开(公告)号：US20080052901A1
公开(公告)日：2008-03-06
申请号：US11889403
申请日：2007-08-13
CPC分类号： H01L21/67115 , H01L21/67103 , H01L21/68721 , H01L29/1608 , H01L29/6606 , Y10T29/49117 , Y10T29/49124
摘要： A method of manufacturing a semiconductor device, includes increasing adherence between a susceptor as a heating element, and a semiconductor substrate disposed on the susceptor, by using an adherence increasing mechanism, or increasing heat transmitted to a semiconductor substrate, which is disposed on a susceptor as a heating element, by using a transmitted-heat increasing mechanism; and heating the semiconductor substrate to have a predetermined temperature by heating the susceptor. The adherence increasing mechanism may include the susceptor and one of a heavy-weight stone disposed on the semiconductor substrate, a cap disposed on the semiconductor substrate and engaged with the susceptor, and an adhesive layer provided between the susceptor and the semiconductor substrate. The transmitted-heat increasing mechanism may include the susceptor and small pieces which are disposed on the semiconductor substrate and have radiated-light absorption ability. The susceptor may hold a plurality of the semiconductor substrates in a stacked form.
摘要翻译： 一种制造半导体器件的方法包括通过使用附着增加机构增加作为加热元件的基座和设置在基座上的半导体基板之间的粘附性，或者增加传输到半导体基板的热量，该半导体基板设置在基座 作为加热元件，通过使用透热增加机构; 并且通过加热所述基座来加热所述半导体衬底以具有预定温度。 附着增加机构可以包括基座和设置在半导体衬底上的重量级的石块之一，设置在半导体衬底上并与基座接合的帽以及设置在基座和半导体衬底之间的粘合剂层。 透热增加机构可以包括设置在半导体衬底上并具有辐射光吸收能力的基座和小片。 基座可以以堆叠的形式保持多个半导体衬底。
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公开(公告)号：US08703626B2
公开(公告)日：2014-04-22
申请号：US11889403
申请日：2007-08-13
IPC分类号： H01L21/00
CPC分类号： H01L21/67115 , H01L21/67103 , H01L21/68721 , H01L29/1608 , H01L29/6606 , Y10T29/49117 , Y10T29/49124
摘要： A method of manufacturing a semiconductor device, includes increasing adherence between a susceptor as a heating element, and a semiconductor substrate disposed on the susceptor, by using an adherence increasing mechanism, or increasing heat transmitted to a semiconductor substrate, which is disposed on a susceptor as a heating element, by using a transmitted-heat increasing mechanism; and heating the semiconductor substrate to have a predetermined temperature by heating the susceptor. The adherence increasing mechanism may include the susceptor and one of a heavy-weight stone disposed on the semiconductor substrate, a cap disposed on the semiconductor substrate and engaged with the susceptor, and an adhesive layer provided between the susceptor and the semiconductor substrate. The transmitted-heat increasing mechanism may include the susceptor and small pieces which are disposed on the semiconductor substrate and have radiated-light absorption ability. The susceptor may hold a plurality of the semiconductor substrates in a stacked form.
摘要翻译： 一种制造半导体器件的方法包括通过使用附着增加机构增加作为加热元件的基座和设置在基座上的半导体基板之间的粘附性，或者增加传输到半导体基板的热量，该半导体基板设置在基座 作为加热元件，通过使用透热增加机构; 并且通过加热所述基座来加热所述半导体衬底以具有预定温度。 附着增加机构可以包括基座和设置在半导体衬底上的重量级的石块之一，设置在半导体衬底上并与基座接合的帽以及设置在基座和半导体衬底之间的粘合剂层。 透热增加机构可以包括设置在半导体衬底上并具有辐射光吸收能力的基座和小片。 基座可以以堆叠的形式保持多个半导体衬底。
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公开(公告)号：US20060214200A1
公开(公告)日：2006-09-28
申请号：US11386850
申请日：2006-03-23
IPC分类号： H01L31/113
CPC分类号： H01L29/7722 , Y10S438/931
摘要： A junction semiconductor device having a drain region comprising a low-resistance layer of a first conductive type formed on one surface of a semiconductor crystal, a source region comprising a low-resistance layer of a first conductive type formed on the other surface of the semiconductor crystal, a gate region of a second conductive type formed on the periphery of the source region, a high-resistance layer of a first conductive type between the source region and the drain region, and a recombination-inhibiting semiconductor layer of a second conductive type provided in the vicinity of the surface of the semiconductor crystal between the gate region and the source region.
摘要翻译： 一种结半导体器件，具有包括形成在半导体晶体的一个表面上的第一导电类型的低电阻层的漏极区域，包括形成在半导体的另一个表面上的第一导电类型的低电阻层的源极区域 晶体，形成在源极区域周围的第二导电类型的栅极区域，在源极区域和漏极区域之间的第一导电类型的高电阻层，以及第二导电类型的复合抑制半导体层 设置在栅极区域和源极区域之间的半导体晶体的表面附近。
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公开(公告)号：US07867836B2
公开(公告)日：2011-01-11
申请号：US12203660
申请日：2008-09-03
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L29/7722 , Y10S438/931
摘要： A method for manufacturing a junction semiconductor device having a drain region including a low-resistance layer of a first conductive type formed on one surface of a semiconductor crystal, a source region including a low-resistance layer of a first conductive type formed on the other surface of the semiconductor crystal, a gate region of a second conductive type formed on the periphery of the source region, a high-resistance layer of a first conductive type between the source region and the drain region, and a recombination-inhibiting semiconductor layer of a second conductive type provided in the vicinity of the surface of the semiconductor crystal between the gate region and the source region.
摘要翻译： 一种用于制造具有形成在半导体晶体的一个表面上的具有第一导电类型的低电阻层的漏极区域的结半导体器件的方法，包括形成在另一个上的第一导电类型的低电阻层的源极区域 半导体晶体的表面，形成在源极区域周围的第二导电类型的栅极区域，在源极区域和漏极区域之间的第一导电类型的高电阻层，以及复合抑制半导体层 设置在栅极区域和源极区域之间的半导体晶体的表面附近的第二导电类型。
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公开(公告)号：US07449734B2
公开(公告)日：2008-11-11
申请号：US11386850
申请日：2006-03-23
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/119
CPC分类号： H01L29/7722 , Y10S438/931
摘要： A junction semiconductor device having a drain region including a low-resistance layer of a first conductive type formed on one surface of a semiconductor crystal, a source region including a low-resistance layer of a first conductive type formed on the other surface of the semiconductor crystal, a gate region of a second conductive type formed on the periphery of the source region, a high-resistance layer of a first conductive type between the source region and the drain region, and a recombination-inhibiting semiconductor layer of a second conductive type provided in the vicinity of the surface of the semiconductor crystal between the gate region and the source region.
摘要翻译： 具有形成在半导体晶体的一个表面上的具有第一导电类型的低电阻层的漏极区的结半导体器件，包括形成在半导体的另一个表面上的第一导电类型的低电阻层的源极区域 晶体，形成在源极区域周围的第二导电类型的栅极区域，在源极区域和漏极区域之间的第一导电类型的高电阻层，以及第二导电类型的复合抑制半导体层 设置在栅极区域和源极区域之间的半导体晶体的表面附近。
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公开(公告)号：US20090004790A1
公开(公告)日：2009-01-01
申请号：US12203660
申请日：2008-09-03
IPC分类号： H01L21/337
CPC分类号： H01L29/7722 , Y10S438/931
摘要： A method for manufacturing a junction semiconductor device having a drain region including a low-resistance layer of a first conductive type formed on one surface of a semiconductor crystal, a source region including a low-resistance layer of a first conductive type formed on the other surface of the semiconductor crystal, a gate region of a second conductive type formed on the periphery of the source region, a high-resistance layer of a first conductive type between the source region and the drain region, and a recombination-inhibiting semiconductor layer of a second conductive type provided in the vicinity of the surface of the semiconductor crystal between the gate region and the source region.
摘要翻译： 一种用于制造具有形成在半导体晶体的一个表面上的具有第一导电类型的低电阻层的漏极区域的结半导体器件的方法，包括形成在另一个上的第一导电类型的低电阻层的源极区域 半导体晶体的表面，形成在源极区域周围的第二导电类型的栅极区域，在源极区域和漏极区域之间的第一导电类型的高电阻层，以及复合抑制半导体层 设置在栅极区域和源极区域之间的半导体晶体的表面附近的第二导电类型。
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