公开(公告)号：US5555522A

公开(公告)日：1996-09-10

申请号：US434442

申请日：1995-05-03

申请人： Kenji Anami ,  Shigeki Ohbayashi ,  Osamu Inoue

发明人： Kenji Anami ,  Shigeki Ohbayashi ,  Osamu Inoue

IPC分类号： G01R31/28 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24 ,  H01L21/82 ,  H01L21/8244 ,  H01L27/11 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C29/835 ,  G11C29/24

摘要： A semiconductor memory comprising a flip-flop circuit, a redundant memory cell row and column, a specific address detecting gate, a transistor, a sense amplifier and a data output buffer. The receipt of a supply potential causes the flip-flop circuit to generate previously stored output status representing the use or the nonuse of the redundant memory cell row and column. Upon detection of a specific address by the specific address detecting gate, the transistor effects a switching operation causing the output status generated by the flip-flop circuit to be output to the outside via the transistor, sense amplifier and data output buffer. This allows the use or the nonuse of the redundant bits to be verified efficiently.

摘要翻译： 一种半导体存储器，包括触发器电路，冗余存储单元行和列，特定地址检测门，晶体管，读出放大器和数据输出缓冲器。 接收到电源电位使得触发器电路产生表示冗余存储器单元行和列的使用或不使用的先前存储的输出状态。 在通过特定地址检测门检测到特定地址时，晶体管进行切换操作，使得由触发器电路产生的输出状态经由晶体管，读出放大器和数据输出缓冲器输出到外部。 这允许有效地验证冗余位的使用或不使用。

公开(公告)号：US5223744A

公开(公告)日：1993-06-29

申请号：US680185

申请日：1991-04-03

申请人： Shigeki Ohbayashi ,  Atsushi Ohba ,  Kenji Anami

发明人： Shigeki Ohbayashi ,  Atsushi Ohba ,  Kenji Anami

IPC分类号： G11C11/413 ,  G05F3/22 ,  G11C11/401 ,  G11C11/407 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  H03K19/003 ,  H03K19/086

CPC分类号： H03K19/086 ,  G05F3/227

摘要： A semiconductor integrated circuit includes a plurality of emitter-coupled logic (ECL) circuits (10) and circuitry (5, 6a, 6b) generating a reference potential to determine the logic threshold value of the ECL circuits. The reference potential generating circuitry is provided near a first pad (2) for a first supply voltage (VCC) and includes a circuit (5) for generating a first reference potential from the first supply voltage, and a circuit (6a, 6b) provided one for each the group of ECL circuits and provided near an associated ECL circuit group for generating a second reference potential from the first reference potential to generate a reference potential as the logic threshold potential of a corresponding ECL circuit. The semiconductor integrated circuit further includes a first clamping potential generating circuit (16) provided near the first pad for generating a first clamping potential in response to the first supply voltage, and a first clamping circuit (113) for clamping the potential at a node of current/voltage converting resistance element (205, 206) included in the ECL circuits at a first voltage in response to the first clamping potential.

摘要翻译： 半导体集成电路包括多个发射极耦合逻辑（ECL）电路（10）和产生用于确定ECL电路的逻辑阈值的参考电位的电路（5,6a，6b）。 参考电位产生电路设置在用于第一电源电压（VCC）的第一焊盘（2）附近，并且包括用于从第一电源电压产生第一参考电位的电路（5）和提供的电路（6a，6b） 在每个ECL电路组中一个，并且在相关联的ECL电路组附近提供用于从第一参考电位产生第二参考电位，以产生参考电位作为相应的ECL电路的逻辑阈值电位。 半导体集成电路还包括：第一钳位电位产生电路（16），设置在第一焊盘附近，用于响应于第一电源电压产生第一钳位电位;以及第一钳位电路（113），用于将电位钳位在 电流/电压转换电阻元件（205,206）响应于第一钳位电位而以第一电压包含在ECL电路中。

公开(公告)号：US5280441A

公开(公告)日：1994-01-18

申请号：US725782

申请日：1991-07-09

申请人： Tomohisa Wada ,  Kenji Anami ,  Shuji Murakami

发明人： Tomohisa Wada ,  Kenji Anami ,  Shuji Murakami

IPC分类号： G11C11/417 ,  G11C7/18 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C11/41 ,  H01L27/108 ,  G11C5/06

CPC分类号： H01L27/10817 ,  G11C7/18

摘要： A plurality of bit line signal IO lines L1, /L1, . . . Ln and /Ln are arranged on a memory cell array. These bit line signal IO lines are arranged to cross respective bit lines BL1, /BL1, . . . BLn and /BLn, and are connected to the corresponding bit lines, respectively. Each bit line signal IO line has an end extended to an end, in a direction perpendicular to the bit line, of a memory cell array, and is coupled at the end to a bit line peripheral circuit. Although bit line peripheral circuits could be arranged only at upper and lower ends of the bit lines in the prior art, the bit line peripheral circuits can be arranged also at the ends of the bit line signal IO lines in the invention. This can increase a degree of freedom in a layout for the bit line peripheral circuits, and thus the bit line peripheral circuits can be dispersedly arranged in a larger area.

摘要翻译： 多个位线信号IO线L1，/ L1，...。 。 。 Ln和/ Ln布置在存储单元阵列上。 这些位线信号IO线被布置成与相应的位线BL1，/ BL1交叉。 。 。 BLn和/ BLn，分别连接到相应的位线。 每个位线信号IO线具有延伸到存储单元阵列的垂直于位线的方向的一端的端部，并且在端部耦合到位线外围电路。 尽管现有技术中位线外围电路只能位于位线的上端和下端，但位线外围电路也可以布置在本发明的位线信号IO线的端部。 这可以增加位线外围电路的布局的自由度，并且因此位线外围电路可以分散地布置在更大的区域中。

公开(公告)号：USRE32993E

公开(公告)日：1989-07-18

申请号：US97770

申请日：1987-09-17

申请人： Kenji Anami ,  Masahiko Yoshimoto ,  Hirofumi Shinohara ,  Osamu Tomisawa

发明人： Kenji Anami ,  Masahiko Yoshimoto ,  Hirofumi Shinohara ,  Osamu Tomisawa

IPC分类号： G11C11/417 ,  G11C5/02 ,  G11C5/06 ,  G11C8/12 ,  G11C8/14 ,  G11C11/41

CPC分类号： G11C5/06 ,  G11C5/02 ,  G11C8/12 ,  G11C8/14

摘要： A semiconductor memory device is improved as regards current consumption and access time by dividing the memory cells into a plurality of columner groups and providing group selecting lines. Front-end word lines flow resistance are connected to outputs of row decoders, and AND gates receive selecting signals on the group selecting lines and the outputs of the front-end word lines. Word lines of a comparatively short length are connected to the AND outputs.

公开(公告)号：US4521704A

公开(公告)日：1985-06-04

申请号：US462204

申请日：1983-01-31

申请人： Hirofumi Shinohara ,  Osamu Tomisawa ,  Kenji Anami ,  Masahiko Yoshimoto

发明人： Hirofumi Shinohara ,  Osamu Tomisawa ,  Kenji Anami ,  Masahiko Yoshimoto

IPC分类号： G11C11/417 ,  H03F3/26 ,  H03F3/45 ,  H03K5/02

CPC分类号： H03F3/265 ,  H03F3/45076 ,  H03F2203/45318 ,  H03F2203/45394

摘要： A differential amplifying circuit includes a pair of main amplifying circuits (5a, 5b) each having at least three input terminals and at least one output terminal, and a pair of auxiliary amplifying circuits (6a, 6b) each having at least one input terminal. Complimentary inputs (D1, D1) are connected to the input terminals of said pair of auxiliary amplifying circuits (6a, 6b), the outputs (D2, D2) of the main amplifying circuits (5a, 5b) are connected as crossing feedback inputs to at least a pair of input terminals of said pair of main amplifying circuits (5a, 5b), the complimentary inputs (D2, D2) are also connected to the other at least one pair of input terminals, and the outputs of said auxiliary amplifying circuits (6a, 6b) are further connected to the further at least pair of input terminals.

摘要翻译： 差分放大电路包括一对主放大电路（5a，5b），每一个具有至少三个输入端和至少一个输出端，以及一对辅助放大电路（6a，6b），每一个具有至少一个输入端。 免费输入（D1，＆amp; upbar＆D）连接到所述一对辅助放大电路（6a，6b）的输入端，主放大电路（5a，5b）的输出（D2，＆amp; upbar＆D） 输入到所述一对主放大电路（5a，5b）中的至少一对输入端，所述互补输入（D2，＆amp;上和下）也连接到另一个至少一对输入端，并且所述输出 辅助放大电路（6a，6b）进一步连接到另外的至少一对输入端。

公开(公告)号：US5248946A

公开(公告)日：1993-09-28

申请号：US805144

申请日：1991-12-11

申请人： Shuji Murakami ,  Atsushi Ohba ,  Kenji Anami

发明人： Shuji Murakami ,  Atsushi Ohba ,  Kenji Anami

IPC分类号： G11C11/419 ,  H03F3/34 ,  H03F3/347 ,  H03F3/45

CPC分类号： H03F3/45076

摘要： An amplifier circuit of a symmetrical type is implemented with load transistors 1, 3, 5, 6 and input transistors 2, 4. Load transistors 1, 5 and input transistor 2 constitute a first inverter, and load transistors 3, 6 and input transistor 4 constitute a second inverter. A change in the output potential of each inverter is transmitted to a load transistor of the other inverter and increases the fluctuation of the potential of an output signal. A transistor 9 or 10 for current control is arranged between an input transistor and ground or between a load transistor and a power supply. The transistor 9 or 10 for current control interrupts through current when operation of the amplifier circuit is unnecessary and enhances the gain when the amplifier circuit is on operation. The gain is enhanced by setting the conductance of the load transistor and the conductance of the input transistor on predetermined conditions. Furthermore, an offset voltage caused in each amplifier circuit is canceled out by connecting two sets of symmetrical-type amplifier circuits.

公开(公告)号：US5193074A

公开(公告)日：1993-03-09

申请号：US646910

申请日：1991-01-28

申请人： Kenji Anami

发明人： Kenji Anami

IPC分类号： G11C11/41 ,  G11C8/14 ,  G11C11/401 ,  G11C11/407

CPC分类号： G11C8/14

摘要： A memory cell array of this semiconductor memory device includes a plurality of memory cells each having one transistor and one capacitor and is divided into a plurality of large memory cell groups, and each of the large memory cell groups is further divided into a plurality of small memory cell groups. A plurality of main row-selecting lines, a plurality of sub row-selecting lines and a plurality of word lines are provided in the memory cell array, each of the large memory cell groups and each of the small memory cell groups, respectively. Main global decoders select one of the main row-selecting lines in response to an internal address signal. Sub global decoders select a sub row-selecting line associated with the selected main row-selecting line in the large memory cell group selected by a large memory cell group selecting signal. Local decoders select a word line associated with the selected sub row-selecting line in the small memory cell group selected by a small memory cell group selecting signal.

摘要翻译： 该半导体存储器件的存储单元阵列包括多个存储单元，每个存储单元具有一个晶体管和一个电容器，并被分成多个大存储单元组，并且每个大存储单元组进一步分为多个小 记忆单元组。 多个主行选择线，多个子行选择线和多个字线分别设置在存储单元阵列中，每个大存储单元组和每个小存储单元组。 主要全局解码器响应内部地址信号选择主行选择行之一。 子全局解码器选择与由大存储器单元组选择信号选择的大存储单元组中的所选主行选择线相关联的子行选择线。 本地解码器选择与由小存储单元组选择信号选择的小存储单元组中的所选子行选择线相关联的字线。

公开(公告)号：US4554646A

公开(公告)日：1985-11-19

申请号：US542388

申请日：1983-10-17

申请人： Masahiko Yoshimoto ,  Tsutomu Yoshihara ,  Kenji Anami ,  Hirofumi Shinohara

发明人： Masahiko Yoshimoto ,  Tsutomu Yoshihara ,  Kenji Anami ,  Hirofumi Shinohara

IPC分类号： G11C8/12 ,  G11C8/14 ,  G11C11/40

CPC分类号： G11C8/14 ,  G11C8/12

摘要： A memory matrix is segmented in the direction of columns into a plurality of groups of memory cells. The memory cells are accessible through respective preceding word lines each of which is provided for each of the rows of the matrix and commonly to all of the groups of the memory cells and group word lines each of which is provided per group and per row, so that a path for column current is set up during access time only in the column which belongs to a particular group including a particular memory to be accessed.

摘要翻译： 存储器矩阵在列的方向上分割成多组存储器单元。 存储器单元可以通过各自的前面的字线访问，每个字线是为矩阵的每一行提供的，并且通常是存储器单元的所有组以及每个组和每行提供的组字线，因此 在访问时间期间仅在属于包括要访问的特定存储器的特定组的列中建立列电流的路径。

公开(公告)号：US5744838A

公开(公告)日：1998-04-28

申请号：US455243

申请日：1995-05-31

申请人： Ryuichi Matsuo ,  Kenji Anami

发明人： Ryuichi Matsuo ,  Kenji Anami

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/08 ,  H01L27/088 ,  H01L29/78 ,  H01L23/62

CPC分类号： H01L27/0255

摘要： Obtained is a semiconductor device which can effectively prevent a gate oxide film from deterioration or breaking caused by plasma charged particles which are accumulated in a wiring layer in plasma etching thereof, even if an antenna ratio is increased. In this semiconductor device, an impurity diffusion layer forming a resistor and a diode is interposed between a gate electrode layer of a field-effect transistor of an internal circuit other than an initial input stage circuit and a first wiring layer for transmitting a circuit signal to the gate electrode layer. Thus, plasma charged particles which are accumulated in the first wiring layer in plasma etching thereof are absorbed by the impurity diffusion layer, whereby no surge voltage is applied to the gate electrode layer which is connected with the first wiring layer. Thus, the gate oxide film which is positioned under the gate electrode layer is prevented from breaking or deterioration.

摘要翻译： 所获得的是即使天线比率增加，也可以有效地防止栅极氧化膜由于等离子体蚀刻而被积聚在布线层中的等离子体带电粒子导致的劣化或破坏的半导体器件。 在该半导体装置中，在初始输入级电路以外的内部电路的场效应晶体管的栅电极层和用于将电路信号发送到第一布线层之间插入形成电阻器和二极管的杂质扩散层 栅电极层。 因此，在等离子体蚀刻中积聚在第一布线层中的等离子体带电粒子被杂质扩散层吸收，由此没有浪涌电压施加到与第一布线层连接的栅极电极层。 因此，防止位于栅电极层下方的栅极氧化膜破裂或劣化。

公开(公告)号：US5694354A

公开(公告)日：1997-12-02

申请号：US708063

申请日：1996-08-12

申请人： Kenji Anami ,  Toshihiko Hirose ,  Shuji Murakami ,  Kojiro Yuzuriha

发明人： Kenji Anami ,  Toshihiko Hirose ,  Shuji Murakami ,  Kojiro Yuzuriha

IPC分类号： G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  H01L21/8244 ,  H01L27/11 ,  G11C11/00

CPC分类号： H01L27/11 ,  G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  H01L27/1108

摘要： A static random access memory (SRAM) is disclosed having a single bit line configuration. One memory cell includes access gate transistors Q5, Q6 connected in series between a data storage circuit 1 and a single bit line BL. In a writing operation, the gate electrodes of the transistors Q5, Q6 are boosted to a level exceeding the supply voltage by a X word line boosting circuit 7 and a Y word line boosting circuit 8 to bring the data storage circuit to an unstable data storage state in a memory cell selected by a row address signal and a column address signal. Data writing is carried out only in a desired memory cell, and erroneous data writing to other memory cells is prevented.

摘要翻译： 公开了具有单个位线配置的静态随机存取存储器（SRAM）。 一个存储单元包括串联连接在数据存储电路1和单个位线BL之间的存取栅极晶体管Q5，Q6。 在写入操作中，晶体管Q5，Q6的栅电极通过X字线升压电路7和Y字线升压电路8升压到超过电源电压的电平，以使数据存储电路处于不稳定的数据存储 状态在由行地址信号和列地址信号选择的存储单元中。 仅在期望的存储单元中执行数据写入，并且防止对其它存储单元的错误数据写入。