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1.发明授权Semiconductor integrated circuit device having a sampling signal generation circuit 有权具有采样信号发生电路的半导体集成电路装置公开(公告)号：US06954096B2
公开(公告)日：2005-10-11
申请号：US10760489
申请日：2004-01-21
申请人： Kenji Ito , Takuya Harada , Hirofumi Isomura
发明人： Kenji Ito , Takuya Harada , Hirofumi Isomura
CPC分类号： H02M7/48 , H02M2001/0012 , H02P7/29
摘要： A semiconductor integrated circuit device is provided to reduce the adverse effect of PWM noise occurring in a PWM driving section on an analog voltage processing section in an IC, in which digital and analog circuits are combined on a single chip. A sampling signal generation circuit outputs a sampling signal St to an A/D converter at a predetermined time when “delay time td+allowance time ta” has elapsed from a start signal Sp. The delay time td is shorter than “the minimum time width of H level of PWM signal SPWM1−allowance time ta”. The delay time td is also time from the variation of level of the PWM signal SPWM1 to actual variation in the passage of current through a power section.
摘要翻译： 提供了一种半导体集成电路器件，以减少在PWM驱动部分中产生的PWM噪声对IC中的模拟电压处理部分的不利影响，其中数字和模拟电路组合在单个芯片上。 当从起始信号Sp经过“延迟时间td +容许时间ta”的预定时间时，采样信号产生电路将采样信号St输出到A / D转换器。 延迟时间td短于“PWM信号SPWM 1的容许时间ta”的H电平的最小时间宽度。 延迟时间td也是从PWM信号SPWM 1的电平变化到通过功率部分的电流通过的实际变化的时间。
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公开(公告)号：US6054876A
公开(公告)日：2000-04-25
申请号：US118072
申请日：1998-07-17
申请人： Masakiyo Horie , Hirofumi Isomura , Takuya Harada
发明人： Masakiyo Horie , Hirofumi Isomura , Takuya Harada
IPC分类号： H03F3/30 , H03F3/45 , H03F3/68 , H03K19/0185 , H03K19/0175 , H03K17/687 , H03K19/003 , H03K19/094
CPC分类号： H03F3/3032 , H03F3/45183 , H03K19/018521 , H03F2203/45641 , H03F2203/45674
摘要： A buffer circuit includes a signal input terminal and a signal output terminal. A first operational amplifier includes a differential amplifier circuit having an input transistor of an N-channel MOS type. The first operational amplifier has an inverting input terminal and an output terminal connected to each other. The first operational amplifier has a non-inverting input terminal connected to the signal input terminal. A second operational amplifier includes a differential amplifier circuit having an input transistor of a P-channel MOS type. The second operational amplifier has an inverting input terminal and an output terminal connected to each other. The second operational amplifier has a non-inverting input terminal connected to the signal input terminal. A first switching device operates for connecting the output terminal of the first operational amplifier to the signal output terminal when a voltage of an input signal applied to the signal input terminal is in a range where the first operational amplifier is operative. A second switching device operates for connecting the output terminal of the second operational amplifier to the signal output terminal when the voltage of the input signal applied to the signal input terminal is in a range where the second operational amplifier is operative.
摘要翻译： 缓冲电路包括信号输入端和信号输出端。 第一运算放大器包括具有N沟道MOS型输入晶体管的差分放大器电路。 第一运算放大器具有彼此连接的反相输入端子和输出端子。 第一运算放大器具有连接到信号输入端的非反相输入端。 第二运算放大器包括具有P沟道MOS型输入晶体管的差分放大器电路。 第二运算放大器具有相互连接的反相输入端和输出端。 第二运算放大器具有连接到信号输入端的非反相输入端。 当施加到信号输入端的输入信号的电压处于第一运算放大器工作的范围时，第一开关装置用于将第一运算放大器的输出端连接到信号输出端。 当施加到信号输入端的输入信号的电压处于第二运算放大器工作的范围时，第二开关装置用于将第二运算放大器的输出端连接到信号输出端。
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公开(公告)号：US20100161080A1
公开(公告)日：2010-06-24
申请号：US12638163
申请日：2009-12-15
IPC分类号： G05B11/01
CPC分类号： F02D41/2451 , F02D41/2467 , F02D41/2474
摘要： The present invention provides, as one aspect, a control system having sensor units and an electronic control unit. The electronic control unit includes a transmission controlling means which sets a signal line connected to the sensor unit, which is a destination of communication data, to a first state, sets the signal line connected to the sensor unit, which is not the destination, to a second state, and transmits the communication data to the destination via a communication line. The sensor unit includes a reception controlling means which determines a to state of the signal line connecting a sensor to the electronic control unit. When determining that the signal line of the sensor unit is in the first state, the reception controlling means receives the communication data and performs a predetermined process. When determining that the signal line is in the second state, the reception controlling means discards the communication data.
摘要翻译： 作为一个方面，本发明提供一种具有传感器单元和电子控制单元的控制系统。 电子控制单元包括传输控制装置，其将连接到作为通信数据的目的地的传感器单元的信号线设置为第一状态，将连接到不是目的地的传感器单元的信号线设置为 第二状态，并且经由通信线路将通信数据发送到目的地。 传感器单元包括接收控制装置，其确定将传感器连接到电子控制单元的信号线的状态。 当确定传感器单元的信号线处于第一状态时，接收控制装置接收通信数据并执行预定的处理。 当确定信号线处于第二状态时，接收控制装置丢弃通信数据。
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公开(公告)号：US08451091B2
公开(公告)日：2013-05-28
申请号：US12638163
申请日：2009-12-15
CPC分类号： F02D41/2451 , F02D41/2467 , F02D41/2474
摘要： The present invention provides, as one aspect, a control system having sensor units and an electronic control unit. The electronic control unit includes a transmission controlling means which sets a signal line connected to the sensor unit, which is a destination of communication data, to a first state, sets the signal line connected to the sensor unit, which is not the destination, to a second state, and transmits the communication data to the destination via a communication line. The sensor unit includes a reception controlling means which determines a state of the signal line connecting a sensor to the electronic control unit. When determining that the signal line of the sensor unit is in the first state, the reception controlling means receives the communication data and performs a predetermined process. When determining that the signal line is in the second state, the reception controlling means discards the communication data.
摘要翻译： 作为一个方面，本发明提供一种具有传感器单元和电子控制单元的控制系统。 电子控制单元包括传输控制装置，其将连接到作为通信数据的目的地的传感器单元的信号线设置为第一状态，将连接到不是目的地的传感器单元的信号线设置为 第二状态，并且经由通信线路将通信数据发送到目的地。 传感器单元包括接收控制装置，其确定将传感器连接到电子控制单元的信号线的状态。 当确定传感器单元的信号线处于第一状态时，接收控制装置接收通信数据并执行预定的处理。 当确定信号线处于第二状态时，接收控制装置丢弃通信数据。
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公开(公告)号：US07026972B2
公开(公告)日：2006-04-11
申请号：US11059371
申请日：2005-02-17
申请人： Hirofumi Isomura
发明人： Hirofumi Isomura
IPC分类号： H03M1/12
CPC分类号： H03M1/56
摘要： A voltage-to-time conversion circuit compares a ramp-wave voltage, which steps up at a certain gradient, with each of a reference voltage, an input voltage, and a reference voltage, and produces a PB pulsating signal representing the times which the voltages require for having a predetermined relationship to the ramp-wave voltage. An encoder circuit converts the times into coded data items according to the ratios of the times to a common unit time. A normalization circuit determines a conversion characteristic curve on the basis of the coded data items, into which the times required by the reference voltages are converted, and A/D-converted values predefined for the reference voltages, and fits the coded data, into which the time required by the input voltage is converted, to the characteristic curve. Thus, the A/D-converted value of the input voltage Vin is calculated.
摘要翻译： 电压 - 时间转换电路将以一定梯度上升的斜波电压与参考电压，输入电压和参考电压中的每一个进行比较，并且产生代表时间的PB脉动信号， 电压要求具有与斜坡波电压的预定关系。 编码器电路根据时间的比率将公共单位时间的次数转换为编码数据。 归一化电路基于将参考电压所需的时间转换成的编码数据项和对于参考电压预定义的A / D转换值来确定转换特性曲线，并且将编码数据拟合到其中 将输入电压所需的时间转换为特性曲线。 因此，计算输入电压Vin的A / D转换值。
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公开(公告)号：US5818797A
公开(公告)日：1998-10-06
申请号：US908975
申请日：1997-08-08
CPC分类号： G04F10/00
摘要： To provide a time measuring apparatus which is compact and capable of highly accurate measurements, on a semiconductor chip, flip-flops constituting a delayed-signal holding circuit of a first channel and flip-flops constituting a delayed-signal holding circuit of a second channel are disposed alternatingly and in a single row in a circuit region of the delayed-signal holding circuits to latch delayed signals from a pulse-circulating circuit, and flip-flops for latching the same delay signals are mutually adjacent. Due to this, distances between the pulse-circulating circuit and the respective delayed-signal holding circuits become equal, and delay signals having no deviation in delay due to difference in wiring length are supplied to the respective channels, and so uniform measurement can be performed between the respective channels.
摘要翻译： 为了提供紧凑且能够高精度测量的时间测量装置，在半导体芯片上，构成第一通道的延迟信号保持电路的触发器和构成第二通道的延迟信号保持电路的触发器 在延迟信号保持电路的电路区域中交替且单行地设置，以锁存来自脉冲循环电路的延迟信号，并且用于锁存相同延迟信号的触发器相互相邻。 由此，脉冲循环电路和各延迟信号保持电路之间的距离变得相等，并且由于布线长度的差异而没有延迟偏差的延迟信号被提供给各个通道，因此可以进行均匀的测量 在各个通道之间。
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公开(公告)号：US20080197910A1
公开(公告)日：2008-08-21
申请号：US12068763
申请日：2008-02-12
申请人： Hirofumi Isomura
发明人： Hirofumi Isomura
IPC分类号： G05F1/00
CPC分类号： B60H1/00428 , Y02T10/88
摘要： An input processing circuit implemented on a semiconductor integrated circuit includes an input terminal for receiving an input signal, a first diode coupled between the input terminal and a power line, a second diode coupled between the input terminal and a ground line, a first MOSFET having a gate and drain coupled together to the input terminal, and a source coupled to the ground line, a second MOSFET coupled to the first MOSFET to construct a current mirror circuit, a current-to-voltage conversion circuit coupled between the power line and the second MOSFET to convert an electric current flowing through the second MOSFET to a voltage, and a determination circuit configured to determine a state of the input signal based on a level of the output voltage of the current-to-voltage conversion circuit.
摘要翻译： 实现在半导体集成电路上的输入处理电路包括用于接收输入信号的输入端，耦合在输入端和电源线之间的第一二极管，耦合在输入端和地线之间的第二二极管，具有 耦合到输入端子的栅极和漏极以及耦合到接地线的源极，耦合到第一MOSFET的第二MOSFET构成电流镜像电路;电流 - 电压转换电路，耦合在电力线和 第二MOSFET，用于将流过第二MOSFET的电流转换为电压;以及确定电路，被配置为基于电流 - 电压转换电路的输出电压的电平来确定输入信号的状态。
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公开(公告)号：US07109761B2
公开(公告)日：2006-09-19
申请号：US11059389
申请日：2005-02-17
申请人： Hirofumi Isomura
发明人： Hirofumi Isomura
IPC分类号： H03K5/22
CPC分类号： H03K17/302 , H03K3/02337 , H03K5/2481
摘要： A reference voltage and an input signal voltage are applied to gates of FETs each equipped with a LOCOS-drain structure, respectively, and currents according to the voltages are made to flow from a power supply voltage Vbat to drain sides through resistors and sources, respectively. The currents are made to flow in FETs to be converted to voltages. Then, both voltages are compared in a comparator. When a potential of a reference voltage input terminal in the comparator that operates with power provided by a power supply Vcc tends to rise above a predetermined level, a FET is turned on and clamps the voltage so as to suppress its potential rise.
摘要翻译： 将参考电压和输入信号电压分别施加到每个配备有LOCOS-漏极结构的FET的栅极，并且使根据电压的电流分别通过电阻器和源从电源电压Vbat流到漏极侧 。 使电流流过FET以转换为电压。 然后，在比较器中比较两个电压。 当通过由电源Vcc提供的功率进行工作的比较器中的参考电压输入端子的电位趋于上升到高于预定电平时，FET被导通并钳位电压以抑制其电位上升。
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9.发明授权Clock-synchronized serial communication device and semiconductor integrated circuit device 有权时钟同步串行通信设备和半导体集成电路器件公开(公告)号：US06946886B2
公开(公告)日：2005-09-20
申请号：US10760349
申请日：2004-01-21
申请人： Hirofumi Isomura
发明人： Hirofumi Isomura
摘要： In a clock-synchronized serial communication device, a counter counts pulses in a communication clock signal. When the count reaches 8, the counter sets a start signal. With this start signal, a pulse generator outputs the first to fourth signals successively. Received data stored in a receiving shift register is transferred to a received-data processing circuit synchronously with the first signal. The received data is further transferred to a timer-setting value register as a timer-setting value synchronously with the second signal. A timer present value is output from a timer present value register synchronously with the third signal. The timer present value is further written into a transmitting shift register as transmission data synchronously with the fourth signal.
摘要翻译： 在时钟同步的串行通信设备中，计数器对通信时钟信号中的脉冲进行计数。 当计数达到8时，计数器设置启动信号。 利用该起始信号，脉冲发生器连续输出第一至第四信号。 存储在接收移位寄存器中的接收数据与第一信号同步地传送到接收数据处理电路。 所接收的数据被进一步作为与第二信号同步的定时器设定值传送到定时器设定值寄存器。 定时器当前值与第三信号同步地从定时器当前值寄存器输出。 定时器当前值被进一步写入发送移位寄存器作为与第四信号同步的发送数据。
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公开(公告)号：US20050190096A1
公开(公告)日：2005-09-01
申请号：US11059371
申请日：2005-02-17
申请人： Hirofumi Isomura
发明人： Hirofumi Isomura
CPC分类号： H03M1/56
摘要： A voltage-to-time conversion circuit compares a ramp-wave voltage, which steps up at a certain gradient, with each of a reference voltage, an input voltage, and a reference voltage, and produces a PB pulsating signal representing the times which the voltages require for having a predetermined relationship to the ramp-wave voltage. An encoder circuit converts the times into coded data items according to the ratios of the times to a common unit time. A normalization circuit determines a conversion characteristic curve on the basis of the coded data items, into which the times required by the reference voltages are converted, and A/D-converted values predefined for the reference voltages, and fits the coded data, into which the time required by the input voltage is converted, to the characteristic curve. Thus, the A/D-converted value of the input voltage Vin is calculated.
摘要翻译： 电压 - 时间转换电路将以一定梯度上升的斜波电压与参考电压，输入电压和参考电压中的每一个进行比较，并且产生代表时间的PB脉动信号， 电压要求具有与斜坡波电压的预定关系。 编码器电路根据时间的比率将公共单位时间的次数转换为编码数据。 归一化电路基于将参考电压所需的时间转换成的编码数据项和对于参考电压预定义的A / D转换值来确定转换特性曲线，并且将编码数据拟合到其中 将输入电压所需的时间转换为特性曲线。 因此，计算输入电压Vin的A / D转换值。
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