公开(公告)号：US06194778B1

公开(公告)日：2001-02-27

申请号：US08910711

申请日：1997-08-13

申请人： Kenji Ohsawa ,  Kazuhiro Sato ,  Makoto Ito

发明人： Kenji Ohsawa ,  Kazuhiro Sato ,  Makoto Ito

IPC分类号： H01L23495

CPC分类号： H01L23/24 ,  H01L23/495 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/05599 ,  H01L2924/00012

摘要： In a semiconductor chip, electrode pads are formed in a peripheral portion of the chip front surface and the inside of the pad forming region is made an effective device region. An insulating, thick-film protective layer is laminated on the effective device region of the semiconductor chip. Leads are constituted of outer leads that are protected by an insulating film and inner leads that are integral with and extend from the outer leads. External connection terminals are formed on the outer leads, and the tips of the inner leads are connected to the electrode pads of the semiconductor chip. A reinforcement plate is provided so as to surround the semiconductor chip. A peripheral space of the semiconductor chip is charged with a sealing resin. According to a second aspect of the invention, a semiconductor chip has electrode pads on the chip front surface and disposed inside a conductive outer ring. A film circuit is disposed on the chip front surface side. External connection terminals are formed on the film circuit so as to project therefrom. First leads electrically connect part of the electrode pads to part of the external connection terminals. A second lead electrically connects a grounding or power supply electrode pad to the outer ring, and a third lead electrically connects a grounding or power supply external connection terminal to the outer ring. A conductive stage is bonded to the chip back surface and the outer ring through respective conductive bonding layers.

公开(公告)号：US6093970A

公开(公告)日：2000-07-25

申请号：US361955

申请日：1999-07-27

申请人： Kenji Ohsawa ,  Makoto Ito ,  Yasushi Otsuka ,  Kazuhiro Sato

发明人： Kenji Ohsawa ,  Makoto Ito ,  Yasushi Otsuka ,  Kazuhiro Sato

IPC分类号： H01L23/24 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H01L23/48

CPC分类号： H01L24/50 ,  H01L23/24 ,  H01L23/3107 ,  H01L23/495 ,  H01L23/49572 ,  H01L23/4985 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/3025 ,  H01L2924/351

摘要： An improved semiconductor device and method of manufacturing employs interconnecting films on film circuit as ground lines which extend to the periphery of the film circuit where there is a further connection to a conductive reinforcing plate 25. Advantageously, the conductive reinforcing plate reduces electrical noise from interfering with the semiconductor device and prevents the semiconductor device from radiating undesired signals. The interconnecting films also reduce cross-talk between signal lines of the semiconductor device.

摘要翻译： 改进的半导体器件和制造方法在薄膜电路上使用互连膜作为接地线，其延伸到膜电路的外围，其中进一步连接到导电加强板25.有利地，导电加强板减少电噪声干扰 与半导体器件并且防止半导体器件辐射不期望的信号。 互连膜还减少了半导体器件的信号线之间的串扰。

公开(公告)号：US5945741A

公开(公告)日：1999-08-31

申请号：US812358

申请日：1997-03-05

申请人： Kenji Ohsawa ,  Makoto Ito ,  Yasushi Otsuka ,  Kazuhiro Sato

发明人： Kenji Ohsawa ,  Makoto Ito ,  Yasushi Otsuka ,  Kazuhiro Sato

IPC分类号： H01L23/24 ,  H01L23/495 ,  H01L23/48

CPC分类号： H01L24/50 ,  H01L23/24 ,  H01L23/49572 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/351

摘要： A semiconductor device employs interconnecting films on film circuit as ground lines which extend to the periphery of the film circuit where there is a further connection to a conductive reinforcing plate. Advantageously the conductive reinforcing plate reduces electrical noise from interfering with the semiconductor device and prevents the semiconductor device from radiating undesired signals. The interconnecting films also reduce cross-talk between signal lines of the semiconductor device.

摘要翻译： 半导体器件在薄膜电路上使用互连膜作为延伸到薄膜电路的周边的接地线，其中进一步连接到导电加强板。 有利的是，导电加强板可降低干扰半导体器件的电噪声，并防止半导体器件辐射不期望的信号。 互连膜还减少了半导体器件的信号线之间的串扰。

公开(公告)号：US5937278A

公开(公告)日：1999-08-10

申请号：US732817

申请日：1996-10-15

申请人： Makoto Ito ,  Kenji Ohsawa ,  Mutsumi Nagano

发明人： Makoto Ito ,  Kenji Ohsawa ,  Mutsumi Nagano

IPC分类号： H01L21/48 ,  H01L23/495 ,  H01L21/44 ,  H01L21/60

CPC分类号： H01L21/4828 ,  H01L23/49524 ,  H01L2924/0002 ,  H01L2924/16195

摘要： A method of manufacturing a lead frame comprises the steps of preparing a three-layered material comprising a metal base, an etching stopper layer made of a metal material different from that of the metal layer formed on a first surface of the metal base and a chromium layer formed on the etching stopper layer, forming a resist layer having a negative pattern relative to an inner lead to be formed on the chromium layer of the three-layered material, forming an inner lead by plating copper by using the resist layer as a mask, forming an outer lead on the metal base, removing a back of a region in which an inner lead of the metal base is formed by etching, removing the etching stopper layer, and removing the chromium layer.

摘要翻译： 制造引线框架的方法包括以下步骤：制备包括金属基底的三层材料，由与金属基底的第一表面上形成的金属层不同的金属材料制成的蚀刻阻挡层和铬 形成在蚀刻停止层上的层，形成相对于在三层材料的铬层上形成的内部引线具有负图案的抗蚀剂层，通过使用抗蚀剂层作为掩模，通过电镀铜形成内部引线 在金属基底上形成外部引线，通过蚀刻除去金属基底的内部引线的区域的背面，去除蚀刻停止层，以及去除铬层。

公开(公告)号：US5982033A

公开(公告)日：1999-11-09

申请号：US850800

申请日：1997-05-02

申请人： Kenji Ohsawa ,  Makoto Ito

发明人： Kenji Ohsawa ,  Makoto Ito

IPC分类号： H01L23/12 ,  H01L23/495 ,  H05K3/20 ,  H05K3/34 ,  H01L23/48

CPC分类号： H01L24/50 ,  H01L23/49572 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01067 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H05K3/20 ,  H05K3/3473

摘要： According to a method of manufacturing a semiconductor package of the present invention, a plurality of leads and a large number of minute convex portions are respectively formed by plating on a surface of a metal base and in an outer peripheral area of the leads thereon. An insulative film for holding each of the leads is formed. A solder resist film is formed selectively on a portion including the outer peripheral area having the minute convex portions thereon. A projecting electrode is formed on an outer lead portion of each of the leads through an opening of the solder resist film on an outer lead portion of each of the leads. The metal base is selectively removed except a joint portion thereof on an outer periphery to separate the respective leads. Inner lead portions of the leads and a semiconductor chip are jointed together. The joint portion of the metal base is cut off.

摘要翻译： 根据本发明的半导体封装的制造方法，通过在金属基体的表面和引线的外周区域中电镀分别形成多个引线和大量微小的凸部。 形成用于保持每个引线的绝缘膜。 在包括其上具有微小凸部的外周区域的部分上选择性地形成阻焊膜。 通过每个引线的外引线部分上的阻焊膜的开口，在每个引线的外引线部分上形成突出电极。 选择性地除去金属基底，除了外围的接合部分以分离各个引线。 引线的内引线部分和半导体芯片接合在一起。 切断金属基座的接合部分。

公开(公告)号：US5901436A

公开(公告)日：1999-05-11

申请号：US730782

申请日：1996-10-16

申请人： Kenji Ohsawa ,  Makoto Ito

发明人： Kenji Ohsawa ,  Makoto Ito

IPC分类号： C23F1/00 ,  H01L21/48 ,  H01L21/60 ,  H01L23/50 ,  H01R43/00

CPC分类号： H01L21/4828 ,  Y10T29/49121

摘要： Leads are formed on a surface of an etching stop film of a base, and holes are defined in the base and a region of a substrate which corresponds to a lead-forming region is thinned by selective etching on both upper and lower surfaces of the base. A lead holder film having a device hole and an outer lead bonding slit is applied to the upper surface of the base. The thinned region of the substrate is removed by selective etching on the lower surface of the base, and the etching stop film is etched away.

摘要翻译： 引线形成在基底的蚀刻停止膜的表面上，并且在基底中限定孔，并且通过在基底的上表面和下表面上的选择性蚀刻使对应于引线形成区的基底的区域变薄 。 具有器件孔和外部引线接合狭缝的引线保持器膜被施加到基座的上表面。 通过在基底的下表面上的选择性蚀刻去除衬底的变薄区域，蚀刻掉蚀刻停止膜。

公开(公告)号：US06258631B1

公开(公告)日：2001-07-10

申请号：US09408024

申请日：1999-09-29

申请人： Makoto Ito ,  Kenji Ohsawa

发明人： Makoto Ito ,  Kenji Ohsawa

IPC分类号： H01L2144

CPC分类号： H01L24/86 ,  H01L23/24 ,  H01L23/49572 ,  H01L24/45 ,  H01L24/48 ,  H01L24/50 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/73269 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00015

摘要： A semiconductor package provided with a reinforcing plate on the side of the lead joined face of which a chip housing concave portion is formed, a semiconductor chip housed and fixed in the chip housing concave portion of this reinforcing plate, a plurality of leads joined and held on the lead joined face of the reinforcing plate, the inner lead section of which is joined to the semiconductor chip via a bump and in the outer lead section of which a protruded electrode is formed, a solder resist film formed on the lead except the bump formed area and the electrode formed area of this lead and a polyimide film formed on the side of the inner lead section of the lead on the solder resist film and the manufacturing method are disclosed and hereby, the quality of the semiconductor package with ultra-multipin structure is stabilized.

摘要翻译： 一种半导体封装，在其引线接合面的形成有芯片壳体凹部的一侧上设置有加强板，容纳并固定在该加强板的芯片容纳凹部中的半导体芯片，多个引线接合并保持 在加强板的引线接合面上，其内引线部分经由凸块接合到半导体芯片，并且在形成有突出电极的外引线部分中，形成在引线上的阻焊膜，除了凸块 形成区域和该引线的电极形成区域以及在阻焊膜上形成在引线的内部引线部分侧的聚酰亚胺膜和制造方法，因此，公开了具有超多极体的半导体封装的质量 结构稳定。

公开(公告)号：US6104091A

公开(公告)日：2000-08-15

申请号：US53988

申请日：1998-04-02

申请人： Makoto Ito ,  Kenji Ohsawa

发明人： Makoto Ito ,  Kenji Ohsawa

IPC分类号： H01L23/50 ,  H01L23/24 ,  H01L23/495 ,  H01L23/10

CPC分类号： H01L24/86 ,  H01L23/24 ,  H01L23/49572 ,  H01L24/50 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/73269 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15747 ,  H01L2924/181

摘要： A semiconductor package provided with a reinforcing plate on the side of the lead joined face of which a chip housing concave portion is formed, a semiconductor chip housed and fixed in the chip housing concave portion of this reinforcing plate, a plurality of leads joined and held on the lead joined face of the reinforcing plate, the inner lead section of which is joined to the semiconductor chip via a bump and in the outer lead section of which a protruded electrode is formed, a solder resist film formed on the lead except the bump formed area and the electrode formed area of this lead and a polyimide film formed on the side of the inner lead section of the lead on the solder resist film and the manufacturing method are disclosed and hereby, the quality of the semiconductor package with ultra-multipin structure is stabilized.

摘要翻译： 一种半导体封装，在其引线接合面的形成有芯片壳体凹部的一侧上设置有加强板，容纳并固定在该加强板的芯片壳体凹部中的半导体芯片，多个引线接合并保持 在加强板的引线接合面上，其内引线部分经由凸块接合到半导体芯片，并且在形成有突出电极的外引线部分中，形成在引线上的阻焊膜，除了凸块 形成区域和该引线的电极形成区域以及在阻焊膜上形成在引线的内部引线部分侧的聚酰亚胺膜和制造方法，因此，公开了具有超多极体的半导体封装的质量 结构稳定。

公开(公告)号：US6074898A

公开(公告)日：2000-06-13

申请号：US237296

申请日：1999-01-25

申请人： Kenji Ohsawa ,  Makoto Ito

发明人： Kenji Ohsawa ,  Makoto Ito

IPC分类号： H01L23/24 ,  H01L23/36 ,  H01L23/495 ,  H01L23/498 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L24/50 ,  H01L23/24 ,  H01L23/36 ,  H01L23/49572 ,  H01L23/49816 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73253 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15747 ,  H01L2924/181

摘要： A lead frame includes a plurality of leads held by an insulative holding film and each formed of an inner lead portion for being bonded to a semiconductor chip and an outer lead portion, a pad portion formed at an end portion of the outer lead portion, an insulating film formed in a pattern so as to insulate the adjacent leads, a ground film formed on the pad portion and partially on the insulating film and having a wider area as compared with that of the pad portion, and a projecting electrode formed on the ground film.

摘要翻译： 引线框架包括由绝缘保持膜保持的多个引线，每个引线由用于接合到半导体芯片的外部引线部分和外部引线部分形成，形成在外部引线部分的端部处的焊盘部分， 形成在图案上以使相邻引线绝缘的绝缘膜，形成在焊盘部分上并部分地在绝缘膜上并且具有比焊盘部分更宽的区域的接地膜，以及形成在地面上的突出电极 电影。

公开(公告)号：US5886399A

公开(公告)日：1999-03-23

申请号：US714307

申请日：1996-09-18

申请人： Kenji Ohsawa ,  Makoto Ito

发明人： Kenji Ohsawa ,  Makoto Ito

IPC分类号： H01L21/60 ,  H01L23/12 ,  H01L23/16 ,  H01L23/24 ,  H01L23/495 ,  H01L23/48 ,  H01L29/00

CPC分类号： H01L23/16 ,  H01L23/24 ,  H01L2224/45144 ,  H01L2224/48472 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181

摘要： A lead frame includes a plurality of leads held by an insulative holding film and each formed of an inner lead portion for being bonded to a semiconductor chip and an outer lead portion, a pad portion formed at an end portion of the outer lead portion, an insulating film formed in a pattern so as to insulate the adjacent leads, a ground film formed on the pad portion and partially on the insulating film and having a wider area as compared with that of the pad portion, and a projecting electrode formed on the ground film.