公开(公告)号：US20070133284A1

公开(公告)日：2007-06-14

申请号：US11679012

申请日：2007-02-26

申请人： Kevin Conley ,  John Mangan ,  Jeffrey Craig

发明人： Kevin Conley ,  John Mangan ,  Jeffrey Craig

IPC分类号： G11C16/04

CPC分类号： G11C16/107 ,  G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7207 ,  G06F2212/7208 ,  G11C16/10 ,  G11C16/3459 ,  G11C29/82 ,  G11C2216/14

摘要： A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data. The stream of data may further be transformed in order to tend to even out the wear among the blocks of memory. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell.

摘要翻译： 非易失性存储器系统由以块为单位布置的浮动栅极存储单元形成为可以一起可擦除的最小单元的存储器单元。 该系统包括可以单独地或以各种协作组合实现的多个特征。 一个特征是在单独的块中存储其中存储用户数据的大量小区块的特性。 正在访问的用户数据块的这些特征可以在存储器系统由其控制器操作期间被存储在随机存取存储器中以便于访问和更新。 根据另一特征，通过将来自扇区的数据块交替地流向多个存储块，一次存储多个扇区的用户数据。 可以移动流中的数据字节以避免存储器中的不良位置，例如不良列。 也可以通过用于多扇区数据的单一生成电路从流数据生成纠错码。 可以进一步转换数据流，以便趋向于均匀地消除存储器块之间的磨损。 对于具有多个存储器集成电路芯片的存储器系统，又一特征提供了单个系统记录，该系统记录包括每个芯片的容量，并且在寻址块时存储器控制器访问的芯片内分配的用户数据块的连续逻辑地址范围 ，使得容易制造具有不同容量的存储器芯片的存储器系统。 存储器系统的典型形式是可拆卸地与主机系统连接的卡，但是也可以在嵌入在主机系统中的存储器中实现。 存储器单元可以以多种状态操作，以便存储每个单元的多于一位的数据。

公开(公告)号：US20060109712A1

公开(公告)日：2006-05-25

申请号：US11323576

申请日：2005-12-29

申请人： Kevin Conley ,  John Mangan ,  Jeffrey Craig

发明人： Kevin Conley ,  John Mangan ,  Jeffrey Craig

IPC分类号： G11C16/04

CPC分类号： G11C16/107 ,  G06F12/0246 ,  G06F2212/7203 ,  G06F2212/7207 ,  G06F2212/7208 ,  G11C16/10 ,  G11C16/3459 ,  G11C29/82 ,  G11C2216/14

摘要： A non-volatile memory system is formed of floating gate memory cells arranged in blocks as the smallest unit of memory cells that are erasable together. The system includes a number of features that may be implemented individually or in various cooperative combinations. One feature is the storage in separate blocks of the characteristics of a large number of blocks of cells in which user data is stored. These characteristics for user data blocks being accessed may, during operation of the memory system by its controller, be stored in a random access memory for ease of access and updating. According to another feature, multiple sectors of user data are stored at one time by alternately streaming chunks of data from the sectors to multiple memory blocks. Bytes of data in the stream may be shifted to avoid defective locations in the memory such as bad columns. Error correction codes may also be generated from the streaming data with a single generation circuit for the multiple sectors of data. The stream of data may further be transformed in order to tend to even out the wear among the blocks of memory. Yet another feature, for memory systems having multiple memory integrated circuit chips, provides a single system record that includes the capacity of each of the chips and assigned contiguous logical address ranges of user data blocks within the chips which the memory controller accesses when addressing a block, making it easier to manufacture a memory system with memory chips having different capacities. A typical form of the memory system is as a card that is removably connectable with a host system but may alternatively be implemented in a memory embedded in a host system. The memory cells may be operated with multiple states in order to store more than one bit of data per cell.

公开(公告)号：US20050058008A1

公开(公告)日：2005-03-17

申请号：US10917870

申请日：2004-08-13

申请人： Daniel Auclair ,  Jeffrey Craig ,  John Mangan ,  Robert Norman ,  Daniel Guterman ,  Sanjay Mehrotra

发明人： Daniel Auclair ,  Jeffrey Craig ,  John Mangan ,  Robert Norman ,  Daniel Guterman ,  Sanjay Mehrotra

IPC分类号： G06F11/10 ,  G11C16/10 ,  G11C29/50 ,  G11C29/52 ,  G11C7/00

CPC分类号： G11C29/028 ,  G06F11/1068 ,  G06F11/1072 ,  G06F2201/81 ,  G11C16/04 ,  G11C16/10 ,  G11C16/3431 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/52 ,  G11C2029/5004 ,  G11C2029/5006

摘要： Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.

摘要翻译： 正常使用固态存储器（如EEP​​ROM或闪存EEPROM）时会发生软错误。 存储器单元的编程阈值电压从原来的预期电平漂移导致软错误。 在正常读取期间，最初不容易检测到该误差，直到累积漂移变得如此严重以致其发展为硬错误。 数据可能会丢失，如果这些硬错误足够的可以在存储器中发出可用的纠错码。 一种存储器件及其技术能够在整个使用存储器件的过程中检测这些漂移并且将每个存储器单元的阈值电压基本上保持在其预期的水平，从而抵抗将软错误发展成硬错误。

公开(公告)号：US20050083726A1

公开(公告)日：2005-04-21

申请号：US10974366

申请日：2004-10-26

申请人： Daniel Auclair ,  Jeffrey Craig ,  John Mangan ,  Robert Norman ,  Daniel Guterman ,  Sanjay Mehrotra

发明人： Daniel Auclair ,  Jeffrey Craig ,  John Mangan ,  Robert Norman ,  Daniel Guterman ,  Sanjay Mehrotra

IPC分类号： G06F11/10 ,  G11C16/10 ,  G11C29/50 ,  G11C29/52 ,  G11C11/00

CPC分类号： G11C29/028 ,  G06F11/1068 ,  G06F11/1072 ,  G06F2201/81 ,  G11C16/04 ,  G11C16/10 ,  G11C16/3431 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/52 ,  G11C2029/5004 ,  G11C2029/5006

摘要： Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.

摘要翻译： 正常使用固态存储器（如EEP​​ROM或闪存EEPROM）时会发生软错误。 存储器单元的编程阈值电压从原来的预期电平漂移导致软错误。 在正常读取期间，最初不容易检测到该误差，直到累积漂移变得如此严重以致其发展为硬错误。 数据可能会丢失，如果这些硬错误足够的可以在存储器中发出可用的纠错码。 一种存储器件及其技术能够在整个使用存储器件的过程中检测这些漂移并且将每个存储器单元的阈值电压基本上保持在其预期的水平，从而抵抗将软错误发展成硬错误。

公开(公告)号：US20050232407A1

公开(公告)日：2005-10-20

申请号：US11084853

申请日：2005-03-18

申请人： Jeffrey Craig ,  Mark Erickson ,  Mark Kanode ,  Seetharaman Khadri

发明人： Jeffrey Craig ,  Mark Erickson ,  Mark Kanode ,  Seetharaman Khadri

IPC分类号： H04M7/00 ,  H04Q3/00

CPC分类号： H04L45/02 ,  H04Q3/0025

摘要： Methods, systems, and computer program products for managing and selectively distributing routing information in a routing node are disclosed. In one implementation, a method for selectively distributing routing information in a routing node includes organizing internal signaling resources are organized so as to facilitate the efficient mapping of signaling system 7 (SS7) message transfer part (MTP) signaling protocol attributes to Internet protocol (IP)-based signaling resources. A routing status information sharing hierarchy is defined, which enables routing status information to be efficiently shared among members of a signaling mateset group. Members of a signaling mateset replicate and distribute SS7 MTP network management information across non-MTP signaling connections, such as IP connections.

摘要翻译： 公开了用于在路由节点中管理和选择性地分发路由信息的方法，系统和计算机程序产品。 在一个实现中，用于在路由节点中选择性地分发路由信息的方法包括组织内部信令资源被组织以便于信令系统7（SS7）消息传送部分（MTP）信令协议属性到因特网协议（IP ）的信令资源。 定义路由状态信息共享层次结构，使路由状态信息能够在信令伙伴组的成员之间有效共享。 信令伙伴的成员在非MTP信令连接（如IP连接）上复制和分发SS7 MTP网络管理信息。

公开(公告)号：US6049899A

公开(公告)日：2000-04-11

申请号：US113800

申请日：1998-07-08

申请人： Daniel L. Auclair ,  Jeffrey Craig ,  John S. Mangan ,  Robert D. Norman ,  Daniel C. Guterman ,  Sanjay Mehrotra

发明人： Daniel L. Auclair ,  Jeffrey Craig ,  John S. Mangan ,  Robert D. Norman ,  Daniel C. Guterman ,  Sanjay Mehrotra

IPC分类号： G06F11/10 ,  G11C16/10 ,  G11C29/50 ,  G11C29/52 ,  H03M13/00

CPC分类号： G11C29/028 ,  G11C16/10 ,  G11C16/3431 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/52 ,  G06F11/1068 ,  G06F11/1072 ,  G06F2201/81 ,  G11C16/04 ,  G11C2029/5004 ,  G11C2029/5006

摘要： Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.

公开(公告)号：US07437631B2

公开(公告)日：2008-10-14

申请号：US10917870

申请日：2004-08-13

申请人： Daniel L. Auclair ,  Jeffrey Craig ,  John S. Mangan ,  Robert D. Norman ,  Daniel C. Guterman ,  Sanjay Mehrotra

发明人： Daniel L. Auclair ,  Jeffrey Craig ,  John S. Mangan ,  Robert D. Norman ,  Daniel C. Guterman ,  Sanjay Mehrotra

IPC分类号： G11C29/00

CPC分类号： G11C29/028 ,  G06F11/1068 ,  G06F11/1072 ,  G06F2201/81 ,  G11C16/04 ,  G11C16/10 ,  G11C16/3431 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/52 ,  G11C2029/5004 ,  G11C2029/5006

摘要： Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.

摘要翻译： 正常使用固态存储器（如EEP​​ROM或闪存EEPROM）时会发生软错误。 存储器单元的编程阈值电压从原来的预期电平漂移导致软错误。 在正常读取期间，最初不容易检测到该误差，直到累积漂移变得如此严重以致其发展为硬错误。 数据可能会丢失，如果这些硬错误足够的可以在存储器中发出可用的纠错码。 一种存储器件及其技术能够在整个使用存储器件的过程中检测这些漂移并且将每个存储器单元的阈值电压基本上保持在其预期的水平，从而抵抗将软错误发展成硬错误。

公开(公告)号：US07246268B2

公开(公告)日：2007-07-17

申请号：US10051833

申请日：2002-01-16

申请人： Jeffrey Craig ,  John S. Mangan

发明人： Jeffrey Craig ,  John S. Mangan

IPC分类号： G06F11/00

CPC分类号： G11C29/765 ,  G06F12/0246 ,  G06F2212/7205 ,  G11C16/349

摘要： Methods and apparatus for automatically detecting when a memory system has significantly degraded are disclosed. According to one aspect of the present invention, a method for determining a status associated with a memory system which includes a plurality of sectors includes updating a counter, comparing the counter to a threshold value, and generating an appropriate indication when comparing the counter to the threshold value yields a first result. The counter is updated each time a sector is reassigned, and indicates a number of sectors remaining in the memory system. The threshold value indicates a number of sectors which are yet to be reassigned in order for the memory system to be considered as useable, or reliable. The indication is generated when comparing the counter to the threshold value yields a first result to indicate that the memory system is substantially near a failure condition.

摘要翻译： 公开了一种自动检测存储系统何时显着劣化的方法和装置。 根据本发明的一个方面，一种用于确定与包括多个扇区的存储器系统相关联的状态的方法包括：更新计数器，将计数器与阈值进行比较，以及当将计数器与 阈值产生第一个结果。 每次重新分配扇区时，计数器都会更新，并指示存储系统中剩余的扇区数。 阈值指示尚未被重新分配的扇区数，以使存储器系统被认为是可用的或可靠的。 当将计数器与阈值进行比较时产生指示，产生第一结果以指示存储器系统基本上接近故障状态。

公开(公告)号：US5438573A

公开(公告)日：1995-08-01

申请号：US252052

申请日：1994-06-01

申请人： John S. Mangan ,  Robert D. Norman ,  Jeffrey Craig ,  Richard Albert ,  Anil Gupta ,  Jeffrey D. Stai ,  Karl M. J. Lofgren

发明人： John S. Mangan ,  Robert D. Norman ,  Jeffrey Craig ,  Richard Albert ,  Anil Gupta ,  Jeffrey D. Stai ,  Karl M. J. Lofgren

IPC分类号： G06F3/06 ,  G06F11/10 ,  G11C16/10 ,  G11C29/00

CPC分类号： G11C29/765 ,  G06F3/0601 ,  G11C16/102 ,  G06F11/1068 ,  G06F2003/0694

摘要： A file structure employed in a flash electrically erasable and programmable read only memory ("EEPROM") system and aspects of forming and using certain data fields within such a file structure. An array of rows and columns of EEPROM memory cells is divided into blocks of cells that are separately addressable for the purpose of erasing an entire block of cells at the same time. Each block contains several rows of cells with certain columns thereof storing a sector of data, typically 512 bytes of data, and other columns of cells within the same rows being used as spare cells to replace any defective sector data cells and store overhead (header) information about the block and the data sector. Such overhead information includes pointers to locations of any defective sector data cells within the block, whether the block has been mapped out in favor of another block, error correction codes for the sector data and the header information, and other similar types of information.

公开(公告)号：US07616484B2

公开(公告)日：2009-11-10

申请号：US10974366

申请日：2004-10-26

申请人： Daniel L. Auclair ,  Jeffrey Craig ,  John S. Mangan ,  Robert D. Norman ,  Daniel C. Guterman ,  Sanjay Mehrotra

发明人： Daniel L. Auclair ,  Jeffrey Craig ,  John S. Mangan ,  Robert D. Norman ,  Daniel C. Guterman ,  Sanjay Mehrotra

IPC分类号： G11C16/06 ,  G11C16/04 ,  G11C29/00 ,  G08C25/00

CPC分类号： G11C29/028 ,  G06F11/1068 ,  G06F11/1072 ,  G06F2201/81 ,  G11C16/04 ,  G11C16/10 ,  G11C16/3431 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/52 ,  G11C2029/5004 ,  G11C2029/5006

摘要： Soft errors occur during normal use of a solid-state memory such as EEPROM or Flash EEPROM. A soft error results from the programmed threshold voltage of a memory cell being drifted from its originally intended level. The error is initially not readily detected during normal read until the cumulative drift becomes so severe that it develops into a hard error. Data could be lost if enough of these hard errors swamps available error correction codes in the memory. A memory device and techniques therefor are capable of detecting these drifts and substantially maintaining the threshold voltage of each memory cell to its intended level throughout the use of the memory device, thereby resisting the development of soft errors into hard errors.

摘要翻译： 正常使用固态存储器（如EEP​​ROM或闪存EEPROM）时会发生软错误。 存储器单元的编程阈值电压从原来的预期电平漂移导致软错误。 在正常读取期间，最初不容易检测到该误差，直到累积漂移变得如此严重以致其发展为硬错误。 数据可能会丢失，如果这些硬错误足够的可以在存储器中发出可用的纠错码。 一种存储器件及其技术能够在整个使用存储器件的过程中检测这些漂移并且将每个存储器单元的阈值电压基本上保持在其预期的水平，从而抵抗将软错误发展成硬错误。