利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

64 条记录 (耗时 0.034 秒)

    Method of reducing disturbs in non-volatile memory
    3.
    发明申请
    Method of reducing disturbs in non-volatile memory 有权

    公开(公告)号：US20060023507A1

    公开(公告)日：2006-02-02

    申请号：US11238911

    申请日：2005-09-28

    申请人： John Mangan ,  Daniel Guterman ,  George Samachisa ,  Brian Murphy ,  Chi-Ming Wang ,  Khandker Quader

    发明人： John Mangan ,  Daniel Guterman ,  George Samachisa ,  Brian Murphy ,  Chi-Ming Wang ,  Khandker Quader

    IPC分类号： G11C7/10 ,  G11C11/34

    CPC分类号： G11C7/12 ,  G11C16/12 ,  G11C16/3427 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50012 ,  G11C2029/1204

    摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.

    Method of Reducing Disturbs in Non-Volatile Memory
    4.
    发明申请
    Method of Reducing Disturbs in Non-Volatile Memory 有权
    减少非易失性存储器中的干扰的方法

    公开(公告)号：US20070076510A1

    公开(公告)日：2007-04-05

    申请号：US11538521

    申请日：2006-10-04

    申请人： John Mangan ,  Daniel Guterman ,  George Samachisa ,  Brian Murphy ,  Chi-Ming Wang ,  Khandker Quader

    发明人： John Mangan ,  Daniel Guterman ,  George Samachisa ,  Brian Murphy ,  Chi-Ming Wang ,  Khandker Quader

    IPC分类号： G11C8/00

    CPC分类号： G11C7/12 ,  G11C16/12 ,  G11C16/3427 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50012 ,  G11C2029/1204

    摘要： In a non-volatile memory, the displacement current generated in non-selected word lines that results when the voltage levels on an array's bit lines are changed can result in disturbs. Techniques for reducing these currents are presented. In a first aspect, the number of cells being simultaneously programmed on a word line is reduced. In a non-volatile memory where an array of memory cells is composed of a number of units, and the units are combined into planes that share common word lines, the simultaneous programming of units within the same plane is avoided. Multiple units may be programmed in parallel, but these are arranged to be in separate planes. This is done by selecting the number of units to be programmed in parallel and their order such that all the units programmed together are from distinct planes, by comparing the units to be programmed to see if any are from the same plane, or a combination of these. In a second, complementary aspect, the rate at which the voltage levels on the bit lines are changed is adjustable. By monitoring the frequency of disturbs, or based upon the device's application, the rate at which the bit line drivers change the bit line voltage can be adjusted. This can be implemented by setting the rate externally, or by the controller based upon device performance and the amount of data error being generated.

    摘要翻译： 在非易失性存储器中，在阵列位线上的电压电平改变时产生的未选择字线中产生的位移电流可能导致干扰。 提出了减少这些电流的技术。 在第一方面，减少了在字线上同时编程的单元的数量。 在非易失性存储器中，存储器单元阵列由多个单元组成，并且单元被组合成共享公共字线的平面，避免同一平面内的单元的同时编程。 多个单元可以并行编程，但是它们被布置成处于分开的平面中。 这是通过选择并行编程的单元数量及其顺序，使得所有编程在一起的单元都来自不同的平面，通过比较要编程的单元以查看是否来自同一平面，或者组合 这些。 在第二个互补方面，位线上的电压电平改变的速率是可调节的。 通过监视干扰的频率，或者基于设备的应用，可以调整位线驱动器改变位线电压的速率。 这可以通过外部设置速率或由控制器基于设备性能和产生的数据错误量来实现。

    DATA RECOVERY IN A MEMORY SYSTEM USING TRACKING CELLS
    5.
    发明申请
    DATA RECOVERY IN A MEMORY SYSTEM USING TRACKING CELLS 有权
    使用跟踪单元的存储器系统中的数据恢复

    公开(公告)号：US20070226434A1

    公开(公告)日：2007-09-27

    申请号：US11752024

    申请日：2007-05-22

    申请人： Daniel Guterman ,  Stephen Gross ,  Shahzad Khalid ,  Geoffrey Gongwer

    发明人： Daniel Guterman ,  Stephen Gross ,  Shahzad Khalid ,  Geoffrey Gongwer

    IPC分类号： G06F12/00

    CPC分类号： G11C16/26 ,  G11C11/5621 ,  G11C16/349

    摘要： Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used as part of a data recovery operation if there is an error. The tracking cells provide a means to adjust the read parameters to optimum levels in order to reflect the current conditions of the memory system. Additionally, some memory systems that use multi-state memory cells will apply rotation data schemes to minimize wear. The rotation scheme can be encoded in the tracking cells based on the states of multiple tracking cells, which is decoded upon reading.

    摘要翻译： 在存储器系统中使用跟踪单元来改善读取过程。 跟踪单元可以提供数据质量的指示，如果存在错误，可以将其用作数据恢复操作的一部分。 跟踪单元提供了将读取参数调整到最佳水平以便反映存储器系统的当前状况的手段。 另外，使用多状态存储器单元的一些存储器系统将应用旋转数据方案以最小化磨损。 可以基于多个跟踪单元的状态在跟踪单元中编码旋转方案，该单元在读取时被解码。

    Alternate row-based reading and writing for non-volatile memory
    6.
    发明申请
    Alternate row-based reading and writing for non-volatile memory 有权
    用于非易失性存储器的替代行读和写

    公开(公告)号：US20070153583A1

    公开(公告)日：2007-07-05

    申请号：US11321259

    申请日：2005-12-29

    申请人： Daniel Guterman

    发明人： Daniel Guterman

    IPC分类号： G11C11/34

    CPC分类号： G11C16/3418 ,  G11C16/3427

    摘要： A set of storage elements is programmed beginning with a word line WLn adjacent a select gate line for the set. After programming the first word line, the next word line WLn+1 adjacent to the first word line is skipped and the next word line WLn+2 adjacent to WLn+1 is programmed. WLn+1 is then programmed. Programming continues according to the sequence {WLn+4, WLn+3, WLn+6, WLn+5, . . . } until all but the last word line for the set have been programmed. The last word line is then programmed. By programming in this manner, some of the word lines of the set (WLn+1, WLn+3, etc.) have no subsequently programmed neighboring word lines. The memory cells of these word lines will not experience any floating gate to floating gate coupling threshold voltage shift impact due to subsequently programmed neighboring memory cells. The word lines having no subsequently programmed neighbors are read without using offsets or compensations based on neighboring memory cells. The other word lines are read using compensations based on data states within both subsequently programmed neighboring word lines.

    摘要翻译： 一组存储元件从与集合的选择栅极线相邻的字线WLn开始被编程。 在对第一字线进行编程之后，跳过与第一字线相邻的下一个字线WLn + 1，并对与WLn + 1相邻的下一个字线WLn + 2进行编程。 然后编程WLn + 1。 根据序列{WLn + 4，WLn + 3，WLn + 6，WLn + 5，...， 。 。 }直到所有集合的最后一个字线都被编程为止。 然后编程最后一个字线。 通过以这种方式进行编程，组（WLn + 1，WLn + 3等）的一些字线没有随后编程的相邻字线。 这些字线的存储单元将不会经历由于随后编程的相邻存储单元而产生的任何漂浮栅极与浮栅耦合阈值电压偏移的影响。 在不使用基于相邻存储器单元的偏移或补偿的情况下读取没有随后编程的邻居的字线。 使用基于随后编程的相邻字线内的数据状态的补偿来读取其他字线。

    Memory system for legacy hosts
    7.
    发明申请
    Memory system for legacy hosts 有权
    传统主机的内存系统

    公开(公告)号：US20070118713A1

    公开(公告)日：2007-05-24

    申请号：US11286100

    申请日：2005-11-22

    申请人： Daniel Guterman ,  Yoram Cedar ,  Charles Schroter ,  Milton Barrocas ,  Carlos Gonzalez ,  Kevin Conley

    发明人： Daniel Guterman ,  Yoram Cedar ,  Charles Schroter ,  Milton Barrocas ,  Carlos Gonzalez ,  Kevin Conley

    IPC分类号： G06F12/00

    CPC分类号： G06F3/0664 ,  G06F3/0607 ,  G06F3/0661 ,  G06F3/0679 ,  G06F11/1048 ,  G06F13/385

    摘要： A non-volatile memory device is provided with a controller and includes method that controls memory operations and to emulate the memory and communication characteristics of a legacy memory device. In this way, the memory device is compatible with a host that was originally designed to operate the legacy memory device. In particular, the controller performs the emulation to the host taking into account differences such as multibit memory, error correction requirement, memory support of overwrites, and erasable block sizes.

    摘要翻译： 非易失性存储器件具有控制器，并且包括控制存储器操作并模拟传统存储器件的存储器和通信特性的方法。 以这种方式，存储器设备与最初设计用于操作传统存储设备的主机兼容。 特别地，控制器考虑到诸如多位存储器，错误校正要求，覆盖的存储器支持以及可擦除块大小之类的差异，对主机执行仿真。

    BITLINE GOVERNED APPROACH FOR PROGRAM CONTROL OF NON-VOLATILE MEMORY
    9.
    发明申请
    BITLINE GOVERNED APPROACH FOR PROGRAM CONTROL OF NON-VOLATILE MEMORY 有权
    用于非易失性存储器的程序控制的双向管理方法

    公开(公告)号：US20050248989A1

    公开(公告)日：2005-11-10

    申请号：US10839806

    申请日：2004-05-05

    申请人： Daniel Guterman ,  Nima Mokhlesi ,  Yupin Fong

    发明人： Daniel Guterman ,  Nima Mokhlesi ,  Yupin Fong

    IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/12 ,  G11C16/30 ,  G11C16/34

    CPC分类号： G11C16/0483 ,  G11C16/12 ,  G11C16/30 ,  G11C16/3454 ,  G11C16/3459

    摘要： In a system for programming non-volatile storage, technology is disclosed for programming with greater precision and reasonable program times. In one embodiment, a first voltage is applied to a bit line for a first non-volatile storage element in order to inhibit that first non-volatile storage element. A first program voltage is applied to the first non-volatile storage element. For example, a program pulse is applied to a control gate for the first non-volatile storage element. During the program pulse, the bit line is changed from said first voltage to a second voltage, where the second voltage allows the first non-volatile storage element to be programmed.

    摘要翻译： 在用于编程非易失性存储器的系统中，公开了用于以更高的精度和合理的程序时间进行编程的技术。 在一个实施例中，第一电压被施加到用于第一非易失性存储元件的位线，以便禁止第一非易失性存储元件。 第一编程电压被施加到第一非易失性存储元件。 例如，将编程脉冲施加到第一非易失性存储元件的控制栅极。 在编程脉冲期间，位线从所述第一电压改变到第二电压，其中第二电压允许第一非易失性存储元件被编程。